9.3 Power Supply Recommendations

The TLVM13610 buck module is designed to operate over a wide input voltage range of 3 V to 36 V. The

characteristics of the input supply must be compatible with the Absolute Maximum Ratings and Recommended

Operating Conditions in this data sheet. In addition, the input supply must be capable of delivering the required

input current to the loaded regulator circuit. Estimate the average input current with Equation 9.

IIN= VOUT×IOUT

VIN×η

(9)

where

• η is the efficiency.

If the module is connected to an input supply through long wires or PCB traces with a large impedance, take

special care to achieve stable performance. The parasitic inductance and resistance of the input cables can

have an adverse affect on module operation. More specifically, the parasitic inductance in combination with

the low-ESR ceramic input capacitors form an underdamped resonant circuit, possibly resulting in instability or

voltage transients each time the input supply is cycled ON and OFF. The parasitic resistance causes the input

voltage to dip during a load transient. If the module is operating close to the minimum input voltage, this dip can

cause false UVLO triggering and a system reset.

The best way to solve such issues is to reduce the distance from the input supply to the module and use an

electrolytic input capacitor in parallel with the ceramics. The moderate ESR of the electrolytic capacitor helps

damp the input resonant circuit and reduce any overshoot or undershoot at the input. A capacitance in the range

of 47 μF to 100 μF is usually sufficient to provide input parallel damping and helps hold the input voltage steady

during large load transients. A typical ESR of 0.1 Ω to 0.4 Ω provides enough damping for most input circuit

configurations.

9.4 Layout

Proper PCB design and layout is important in high-current, fast-switching module circuits (with high internal

voltage and current slew rates) to achieve reliable device operation and design robustness. Furthermore, the

EMI performance of the module depends to a large extent on PCB layout.

9.4.1 Layout Guidelines

The following list summarizes the essential guidelines for PCB layout and component placement to optimze

DC/DC module performance, including thermals and EMI signature. Figure 9-12 and Figure 9-13 show a

recommended PCB layout for the TLVM13610 with optimized placement and routing of the power-stage and

small-signal components.

• Place input capacitors as close as possible to the VIN pins. Note the dual and symmetrical arrangement

of the input capacitors based on the VIN1 and VIN2 pins located on each side of the module package.

The high-frequency currents are split in two and effectively flow in opposing directions such that the related

magnetic fields contributions cancel each other, leading to improved EMI performance.

– Use low-ESR 1206 or 1210 ceramic capacitors with X7R or X7S dielectric. The module has integrated

dual 0402 input capacitors for high-frequency bypass.

– Ground return paths for the input capacitors must consist of localized top-side planes that connect to the

PGND pads under the module.

– Even though the VIN pins are connected internally, use a wide polygon plane on a lower PCB layer to

connect these pins together and to the input supply.

• Place output capacitors as close as possible to the VOUT pins. A similar dual and symmetrical arrangement

of the output capacitors enables magnetic field cancellation and EMI mitigation.

– Ground return paths for the output capacitors must consist of localized top-side planes that connect to the

PGND pads under the module.

– Even though the VOUT pins are connected internally, use a wide polygon plane on a lower PCB layer to

connect these pins together and to the load, thus reducing conduction loss and thermal stress.

TLVM13610

SLVSH63 – FEBRUARY 2023

www.ti.com

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