TM320LC203 datasheet(58/83 Pages) TI

58 / 83 page

TMS320C203, TMS320C209, TMS320LC203

DIGITAL SIGNAL PROCESSORS

SPRS025B – JUNE 1995 – REVISED AUGUST 1998

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

XF, TOUT, RS, INT1 – INT3, NMI, and BIO timing

switching characteristics over recommended operating conditions for TMS320C203 @ 5 V

(see Figure 13)

PARAMETER

ALTERNATE

SYMBOL

’320C203-40

’320C203-57

’320C203-80

UNIT

SYMBOL

MIN

MAX

MIN

MAX

td(COH-XF)

Delay time, CLKOUT1 high to XF valid

td(XF)

0†

td(COH-TOUT)

Delay time, CLKOUT1 high to TOUT high / low

td(TOUT)

0†

11†

0†

tw(TOUT)

Pulse duration, TOUT high

2H – 12

2H – 9

† Values derived from characterization data and not tested

timing requirements over recommended operating conditions for TMS320C203 @ 5 V

[H = 0.5tc(CO)] (see Figure 14 and Figure 15)

ALTERNATE

SYMBOL

’320C203-40

’320C203-57

’320C203-80

UNIT

SYMBOL

MIN

MAX

MIN

MAX

tsu(RS-CIL)

Setup time, RS before CLKIN low

tsu(RS)CIL

tsu(RS-COL)

Setup time, RS before CLKOUT1 low

tsu(RS)COL

tw(RSL)

Pulse duration, RS low‡

12H

td(RS-RST)

Delay time, RS high to reset-vector fetch

td(EX)

34H

tsu(IN-COLS)

Setup time, INTN before CLKOUT1 low (synchronous)

tsu(IN)COL

th(COLS-IN)

Hold time, INTN after CLKOUT1 low (synchronous)

th(IN)COL

tw(IN)

Pulse duration, INTN low

2H + 18

2H + 16

td(IN-INT)

Delay time, INTN low to interrupt-vector fetch

td(IN)

12H

‡ This parameter assumes the CLKOUT1 to be stable before RS goes active.

tw(TOUT)

td(COH-TOUT)

td(COH-XF)

CLKOUT1

TOUT

Figure 13. XF and TOUT Timing for TMS320C203/LC203

TM320LC203 Datasheet(PDF) 58 Page - Texas Instruments

TM320LC203 Datasheet(HTML) 58 Page - Texas Instruments

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