TM320LC203 datasheet(19/83 Pages) TI

19 / 83 page

TMS320C203, TMS320C209, TMS320LC203

DIGITAL SIGNAL PROCESSORS

SPRS025B – JUNE 1995 – REVISED AUGUST 1998

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

memory (continued)

TMS320C209 (only)

The mask-programmable ROM is located in program memory space. Customers can arrange to have this ROM

programmed with contents unique to any particular application. The ROM is enabled or disabled by the state

of the MP/MC control input upon resetting the device. The ROM occupies the lowest block of program memory

when enabled. When disabled, these addresses are located in the device’s external program memory space.

The ’C209 devices provide two types of RAM: single-access RAM (SARAM) and dual-access RAM (DARAM).

The SARAM requires a full machine cycle to perform a read or a write. However, this is not one large RAM block

in which only one access per cycle is allowed. It is made up of 2K-word size-independent RAM blocks and each

one allows one CPU access per cycle. The CPU can read or write one block while accessing another block at

the same time. The ’C209 processor supports multiple accesses to its SARAM in one cycle as long as they go

to different RAM blocks. With an understanding of this structure, code and data can be appropriately arranged

to improve code performance.

The TMS320C203 includes three registers mapped to internal data space and peripheral registers mapped to

internal I/O space. Figure 1, Table 6, and Table 7 describe these registers and show their respective addresses.

They also show the effects of the memory-control pin BOOT and control bit CNF on the mapping of the

respective memory spaces to on-chip or off-chip memory.

Both of the TMS320C2xx devices include 544

× 16 words of dual-access RAM. The ’C209 device includes

× 16 words of single-access RAM and 4K × 16 words of ROM integrated with CPU. Figure 1, Table 6, and

Table 7 show the mapping of the memory blocks and the appropriate control bits and pins for the ’C203. For

the ’C209 devices, Figure 2, Table 8, and Table 9, show the effects of the memory-control pins MP/MC and

RAMEN, and control bit CNF on the mapping of the respective memory spaces to on-chip or off-chip memory.

On-Chip DARAM

B0 (CNF = 0)

Reserved (CNF = 1)

Interrupts

(External)

0000

0040

External

FDFF

Reserved (CNF = 1)

External (CNF = 0)

FE00

On-Chip DARAM

B0 (CNF = 1)

External (CNF = 0)

FF00

FFFF

Hex

Program

BOOT = 1

Microprocessor Mode

Interrupts

(External)

0000

0040

External

FDFF

FE00

FEFF

On-Chip DARAM

B0 (CNF = 1)

External (CNF = 0)

FF00

FFFF

Hex

Program

BOOT = 0

Microprocessor Mode

(Boot-Loader Enabled)

Memory-Mapped

Registers and

Reserved

0000

Hex

Data

On-Chip

DARAM B2

0060

Reserved

0080

01FF

On-Chip

DARAM B1

0300

0200

0400

Reserved

07FF

External

0800

FFFF

Reserved (CNF = 1)

External (CNF = 0)

003F

FEFF

005F

007F

02FF

03FF

003F

Figure 1. TMS320C203/LC203 Memory Map

TM320LC203 Datasheet(PDF) 19 Page - Texas Instruments

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