TM320LC203 datasheet(13/83 Pages) TI

13 / 83 page

TMS320C203, TMS320C209, TMS320LC203

DIGITAL SIGNAL PROCESSORS

SPRS025B – JUNE 1995 – REVISED AUGUST 1998

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

architectural overview

The ’C2xx advanced Harvard-type architecture maximizes the processing power by maintaining two separate

memory bus structures—program and data—for full-speed execution. This multiple bus structure allows both

data and instructions to be read simultaneously. Instructions to be read support data transfers between the two

spaces. This architecture permits coefficients that are stored in program memory to be read in RAM, thereby,

eliminating the need for a separate coefficient ROM. This, coupled with a four-deep pipeline, allows the

TMS320C2xx to execute most instructions in a single cycle.

status and control registers

Two status registers, ST0 and ST1, contain the status of various conditions and modes. These registers can

be stored in data memory and loaded from data memory, thereby, allowing the status of the machine to be saved

and restored for subroutines.

The load-status-register instruction (LST) is used to write to ST0 and ST1. The store-status-register instruction

(SST) is used to read from ST0 and ST1, except for the INTM bit, which is not affected by the LST instruction.

The individual bits of these registers can be set or cleared when using the SETC and CLRC instructions. Table 4

and Table 5 show the organization of status registers ST0 and ST1, indicating all status bits contained in each.

Several bits in the status registers are reserved and read as logic 1s. Refer to Table 6 for the status register field

definitions.

Table 4. Status and Control Register Zero

ST0

ARP

OVM

INTM

Table 5. Status and Control Register One

ST1

ARB

CNF

SXM

TM320LC203 Datasheet(PDF) 13 Page - Texas Instruments