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APPLICATION INFORMATION

SW NODE RESISTOR

SETTING THE SWITCHING FREQUENCY (PROGRAMMING THE CLOCK OSCILLATOR)

1

* 23 kW

(1)

PROGRAMMING THE RAMP GENERATOR CIRCUIT

UDG-02131

RAMP

COMP

SW

VIN

VIN

SW

COMP

RAMP

d +

T

TPS40060

TPS40061

SLUS543D–DECEMBER 2002–REVISED SEPTEMBER 2004

The TPS40060/61 family of parts allows the user to optimize the PWM controller to the specific application.

The TPS40061 is the controller of choice for synchronous buck designs which will include most applications. It

has two quadrant operation and will source or sink output current. This provides the best transient response.

The TPS40060 operates in one quadrant and sources output current only, allowing for paralleling of converters

and ensures that one converter does not sink current from another converter. This controller also emulates a

standard buck converter at light loads where the inductor current goes discontinuous. At continuous output

inductor currents the controller operates as a synchronous buck converter to optimize efficiency.

The SW node of the converter will be negative during the dead time when both the upper and lower MOSFETs

are off. The magnitude of this negative voltage is dependent on the lower MOSFET body diode and the output

current which flows during this dead time. This negative voltage could affect the operation of the controller,

especially at low input voltages.

Therefore, a 10-Ω resistor must be placed between the lower MOSFET drain and pin 12 (SW) of the controller as

The TPS40060 and TPS40061 have independent clock oscillator and ramp generator circuits. The clock

Equation 1 and the relationship is charted in Figure 2.

The ramp generator circuit provides the actual ramp used by the PWM comparator. The ramp generator provides

voltage feed-forward control by varying the PWM ramp slope with line voltage, while maintaining a constant ramp

magnitude. Varying the PWM ramp directly with line voltage provides excellent response to line variations since

the PWM does not have to wait for loop delays before changing the duty cycle. (See Figure 1).

Figure 1. Voltage Feed-Forward Effect on PWM Duty Cycle

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