TPS40060PWPR datasheet(21/28 Pages) TI

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DESIGN EXAMPLE

1. Calculate maximum and minimum duty cycles

dMIN +

VO(min)

VIN(max)

+ 0.0588

dMAX +

VO(max)

VIN(min)

++ 0.187

(42)

2. Select switching frequency

VO(min)

VIN(max)

tON

TSW

(43)

TSW

+ fSW +

VO(min)

VIN(max)

TON

(44)

fSW +

0.0588

400 ns +

147 kHz

(45)

3. Select∆ I

DI + IO 2 0.2 + 5 2 0.2 + 2.0 A

(46)

4. Calculate the power losses

IRMS + IO

d + 5

0.0588 + 1.2 A

(47)

PCOND + 1.22 0.12 (1 ) 0.007 (150 * 25)) + 0.324 W

(48)

TPS40060

TPS40061

SLUS543D–DECEMBER 2002–REVISED SEPTEMBER 2004

•

Input voltage: 18 VDC to 55 VDC

•

Output voltage: 3.3 V ±2%

•

Output current: 5 A (maximum, steady-state), 7 A (surge, 10-ms duration, 10% duty cycle maximum)

•

Output ripple: 33 mVP-P at 5 A

•

Output load response: 0.3 V => 10% to 90% step load change

•

Operating temperature: –40°Cto85°C

•

fSW = 130 kHz

The switching frequency is based on the minimum duty cycle ratio and the propagation delay of the current limit

comparator. In order to maintain current limit capability, the on time of the upper MOSFET, tON, must be greater

than 330 ns (see Electrical Characteristics table). Therefore

Using 400 ns to provide margin,

Since the oscillator can vary by 10%, decrease fSW, by 10%

fSW =0.9 × 147 kHz = 130 kHz

and therefore choose a frequency of 130 kHz.

In this case ∆I is chosen so that the converter enters discontinuous mode at 20% of nominal load.

Power losses in the high-side MOSFET (Si9407AGY) at 55-VIN where switching losses dominate can be

calculated from Equation 46 through Equation 49.

substituting Equation 30 into Equation 29 yields

and from Equation 31, the switching losses can be determined.

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