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TPS40060PWPR Datasheet(PDF) 13 Page - Texas Instruments |
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TPS40060PWPR Datasheet(HTML) 13 Page - Texas Instruments |
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13 / 28 page ![]() www.ti.com CBPN10 + Qg DV (F) (8) CBP10V + QgSR DV (F) (9) SYNCHRONIZING TO AN EXTERNAL SUPPLY RT(dummy) + 1 fSYNC 17.82 10*6 * 23 kW (10) RKFF + VIN(min) * 3.5 V 65.27 RT(dummy) ) 1502 kW (11) SELECTING THE INDUCTOR VALUE L + VIN * VO VO VIN DI fSW (H) (12) TPS40060 TPS40061 SLUS543D–DECEMBER 2002–REVISED SEPTEMBER 2004 APPLICATION INFORMATION (continued) The 10-V reference pin, BP10V needs to provide energy for the synchronous MOSFET gate drive via the BP10V capacitor. Neglecting any efficiency penalty, the BP10V capacitance is described in Equation 9. The TPS4006x can be synchronized to an external clock through the SYNC pin. The SW node rises on the falling edge of the SYNC signal. The synchronization frequency should be in the range of 20% to 30% higher than its programmed free-run frequency. The clock frequency at the SYNC pin replaces the master clock generated by the oscillator circuit. Pulling the SYNC pin low programs the TPS4006x to freely run at the frequency programmed by RT. Internally, the SYNC pin has a pull-down current between 5 µA and 10 µA. In order to synchronize the device to an external clock signal, the SYNC pin has to be overdriven from the external clock circuit. Normal logic gates or an external MOSFET with a pull-up resistor of 10 kΩ is adequate. Internally there is a delay of between approximately 50 ns and 100 ns from the time the SYNC pin is pulled low and the HDRV signal goes high to turn on the upper MOSFET. Additionally, there is some delay as the MOSFET gate charges to turn on the upper MOSFET, typically between 20 ns and 50 ns. The higher synchronization must be factored in when programming the PWM ramp generator circuit. If the PWM ramp is interrupted by the SYNC pulse, a UVLO condition is declared and the PWM becomes disabled. Typically this is of concern under low-line conditions only. In any case, RKFF needs to be adjusted for the higher switching frequency. In order to specify the correct value for RKFF at the synchronizing frequency, calculate a 'dummy' value for RT that would cause the oscillator to run at the synchronizing frequency. Do not use this value of RT in the design. Use the value of RT(dummy) to calculate the value for RKFF. where: • RT is in kΩ This value of RKFF ensures that UVLO is not engaged when operating at the synchronization frequency. The inductor value determines the magnitude of ripple current in the output capacitors as well as the load current at which the converter enters discontinuous mode. Too large an inductance results in lower ripple current but is physically larger for the same load current. Too small an inductance results in larger ripple currents and a greater number of (or more expensive output capacitors for) the same output ripple voltage requirement. A good compromise is to select the inductance value such that the converter doesn't enter discontinuous mode until the load approximated somewhere between 10% and 30% of the rated output. The inductance value is described in Equation 12. where: • VO is the output voltage •∆I is the peak-to-peak inductor current 13 |
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