6.42

6

71024 CMOS Static RAM

1 Meg (128K x 8-Bit)

Commercial and Industrial Temperature Ranges

Mar.30.21

Timing Waveform of Write Cycle No. 1

(WE Controlled Timing)(1,4,6)

Timing Waveform of Write Cycle No. 2

(CS1 AND CS2 Controlled Timing)(1,4)

NOTES:

1. A write occurs during the overlap of a LOW CS1, HIGH CS2, and a LOW WE.

2. tWR is measured from the earlier of either CS1 or WE going HIGH or CS2 going LOW to the end of the write cycle.

3. During this period, I/O pins are in the output state, and input signals must not be applied.

4. If the CS1 LOW transition or the CS2 HIGH transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS1 and CS2 must

both be active during the tCW write period.

5. Transitionismeasured±200mVfromsteadystate.

6. OE is continuously HIGH. During a WE controlled write cycle with OELOW, tWP must be greater than or equal to tWHZ+ tDW to allow the I/O drivers to turn off and data to be placed

on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified tWP.