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P9028AC Datasheet(PDF) 21 Page - Renesas Technology Corp |
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P9028AC Datasheet(HTML) 21 Page - Renesas Technology Corp |
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21 / 39 page ![]() P9028AC Product Datasheet Revision 1.0.3 21 ©2015IntegratedDeviceTechnology,Inc. APPLICATIONS INFORMATION EXTERNAL COMPONENTS The P9028AC requires a minimum number of external components for proper operation, as indicated in Figure 16, 17 and 18 as well as Table 9, 10 and 11. LDO Input Capacitor (VRECT Capacitors) The LDO input capacitors (VRECT capacitors) should be located as close as possible to the VRECT pins, and ground (PGND). Ceramic capacitors are recommended for their lower ESR and small profile. See Figure 17 and Table 10 for values and type of capacitor. VDD Capacitor The P9028AC has an internal LDO regulator that must have a capacitor connected from the VDD pin to GND. This capacitor should be as close as possible to the VDD pin with a close GND connection. See Figure 17, 18 and Table 10, 11 for values and type of capacitor. Output Capacitor The output capacitor connection to the ground pin (PGND) should be made as short as practical for maximum device performance. Since the LDO has been designed to function with very low ESR capacitors, a ceramic capacitor is recommended for best performance. For better transient response increase the total amount of output capacitance. For 1A load steps, an output capacitance of at least 10µF is recommended. PCB LAYOUT CONSIDERATIONS - For optimum device performance and lowest output phase noise, the following guidelines should be observed. Please contact IDT Inc. for Gerber files that contain the recommended board layout and application note AN883, “P9028AC Layout Guidelines”. - An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Signal traces not related to the P9028AC should be routed away from the IC as much as possible to avoid blocking thermal dissipation paths from the IC to the PCB. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. - Layout and PCB design have a significant influence on the power dissipation capabilities of power management ICs because the surface mount packages used with these devices rely heavily on thermally conductive traces or pads to transfer heat away from the package. Appropriate PC layout techniques should be used to remove the heat due to device power dissipation. - The following general guidelines will be helpful in designing a board layout for lowest thermal resistance: 1. PC board traces with large cross-sectional areas remove more heat. For optimum results, use large-area PCB patterns with wide copper traces, placed on the uppermost side of the PCB. 2. In cases where maximum heat dissipation is required, use double-sided copper planes connected with multiple vias. 3. Thermal vias are needed to provide a thermal path to inner and/or bottom layers of the PCB to remove the heat generated by device power dissipation. POWER DISSIPATION AND THERMAL REQUIREMENTS The P9028AC is offered in a QFN-32 package which has a maximum power dissipation capability of about 1.9W and in a WLCSP package, the maximum power dissipation of which is determined by the number of thermal vias between the package and the printed circuit board. The maximum power dissipation of both packages is defined by the die’s specified maximum operating junction temperature, TJ, of 125°C. The junction temperature rises when the heat generated by the device’s power dissipation goes through the package thermal resistance. The QFN package offers a typical thermal resistance, junction to ambient (ΘJA), of 35OC/W when the PCB layout and surrounding devices are optimized as described in the PCB Layout Considerations section. The WLCSP package has a typical ΘJA of 70ºC/W with 7 thermal vias and 144ºC/W with no thermal vias. Clearly, maximizing the thermal vias is highly recommended. The techniques as noted in the PCB layout section must be followed when designing the printed circuit board layout, as well as the placement of the P9028AC IC package in proximity to other heat- |
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