89C535 datasheet(13/35 Pages) PHILIPS

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Philips Semiconductors

Preliminary specification

89C535/89C536/89C538

CMOS single-chip 8-bit microcontrollers

with FLASH program memory

1997 Jun 05

Interrupt Priority Structure

The 89C535/536/538 has a 6-source two-level interrupt structure

(see Table 7). There are 2 SFRs associated with the interrupts on

the 89C535/536/538. They are the IE and IP. (See Figures 6 and 7.)

The function of the IPH SFR is simple and when combined with the

IP SFR determines the priority of each interrupt. The priority of each

interrupt is determined as shown in the following table:

PRIORITY BITS

INTERRUPT PRIORITY LEVEL

IP.x

INTERRUPT PRIORITY LEVEL

Level 0 (lowest priority)

Level 1 (highest priority)

An interrupt will be serviced as long as an interrupt of equal or

higher priority is not already being serviced. If an interrupt of equal

or higher level priority is being serviced, the new interrupt will wait

until it is finished before being serviced. If a lower priority level

interrupt is being serviced, it will be stopped and the new interrupt

serviced. When the new interrupt is finished, the lower priority level

interrupt that was stopped will be completed.

Table 7.

Interrupt Table

SOURCE

POLLING PRIORITY

REQUEST BITS

HARDWARE CLEAR?

VECTOR ADDRESS

IE0

N (L)1

Y (T)2

03H

TP0

0BH

IE1

N (L)

Y (T)

13H

TF1

1BH

R1, TI

23H

TF2, EXF2

2BH

NOTES:

1. L = Level activated

2. T = Transition activated

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