R16DS0137EU0100 Rev.1.0

Page 20

Apr 13, 2021

RAA210040 Datasheet

▪ Use large copper planes to minimize conduction loss and thermal stress for VIN, VOUT, and PGND. Use

multiple vias to connect the power planes in different layers.

▪ Use a separate SGND plane for components that are connected to SGND. Connect SGND and PGND at a

single point on the top layer as shown in Figure 38.

▪ Use a remote-sensing trace to connect to the point-of-load and achieve tight output voltage regulation. Route

the remote-sensing trace underneath the PGND layer and avoid routing it near noisy planes. Place a 2Ω

resistor close to the output voltage resistor divider and FB pin to damp the noise on the trace.

Figure 36. Layout Example - Top Layer

Figure 37. Layout Example - Bottom Layer

VIN

PGND

PGND

VOUT

CIN

CIN

CIN

U1

PGND

VIN

SGND