DSP56321 datasheet(68/88 Pages) NXP

68 / 88 page

4-2

Electrical Design Considerations

A complicating factor is the existence of three common ways to determine the junction-to-case thermal

resistance in plastic packages.

• To minimize temperature variation across the surface, the thermal resistance is measured from the

junction to the outside surface of the package (case) closest to the chip mounting area when that surface

has a proper heat sink.

• To define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance

is measured from the junction to the point at which the leads attach to the case.

• If the temperature of the package case (TT) is determined by a thermocouple, thermal resistance is

computed from the value obtained by the equation (TJ – TT)/PD.

As noted earlier, the junction-to-case thermal resistances quoted in this data sheet are determined using

the first definition. From a practical standpoint, that value is also suitable to determine the junction

temperature from a case thermocouple reading in forced convection environments. In natural convection,

the use of the junction-to-case thermal resistance to estimate junction temperature from a thermocouple

reading on the case of the package will yield an estimate of a junction temperature slightly higher than

actual temperature. Hence, the new thermal metric, thermal characterization parameter or

JT, has been

defined to be (TJ – TT)/PD. This value gives a better estimate of the junction temperature in natural

convection when the surface temperature of the package is used. Remember that surface temperature

readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the

surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a

40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy.

4.2 Electrical Design Considerations

Use the following list of recommendations to ensure correct DSP operation.

• Provide a low-impedance path from the board power supply to each VCC pin on the DSP and from the

board ground to each GND pin.

• Use at least six 0.01–0.1

µF bypass capacitors positioned as close as possible to the four sides of the

package to connect the VCC power source to GND.

• Ensure that capacitor leads and associated printed circuit traces that connect to the chip VCC and GND

pins are less than 0.5 inch per capacitor lead.

• Use at least a four-layer PCB with two inner layers for VCC and GND.

CAUTION

This device contains protective circuitry to

guard against damage due to high static

voltage or electrical fields. However, normal

precautions are advised to avoid application

of any voltages higher than maximum rated

voltages

this

high-impedance

circuit.

Reliability of operation is enhanced if unused

inputs are tied to an appropriate logic voltage

level (for example, either GND or VCC).

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

DSP56321 Datasheet(PDF) 68 Page - NXP Semiconductors

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