DSP56321 datasheet(75/88 Pages) NXP

75 / 88 page

A-5

Power Consumption Benchmark

;------------------------------------------------------------------------

;

EQUATES for Serial Communications Interface (SCI)

;

;------------------------------------------------------------------------

;

M_STXH EQU $FFFF97

; SCI Transmit Data Register (high)

M_STXM EQU $FFFF96

; SCI Transmit Data Register (middle)

M_STXL EQU $FFFF95

; SCI Transmit Data Register (low)

M_SRXH EQU $FFFF9A

; SCI Receive Data Register (high)

M_SRXM EQU $FFFF99

; SCI Receive Data Register (middle)

M_SRXL EQU $FFFF98

; SCI Receive Data Register (low)

M_STXA EQU $FFFF94

; SCI Transmit Address Register

M_SCR EQU $FFFF9C

; SCI Control Register

M_SSR EQU $FFFF93

; SCI Status Register

M_SCCR EQU $FFFF9B

; SCI Clock Control Register

;

SCI Control Register Bit Flags

M_WDS EQU $7

; Word Select Mask (WDS0-WDS3)

M_WDS0 EQU 0

; Word Select 0

M_WDS1 EQU 1

; Word Select 1

M_WDS2 EQU 2

; Word Select 2

M_SSFTD EQU 3

; SCI Shift Direction

M_SBK EQU 4

; Send Break

M_WAKE EQU 5

; Wakeup Mode Select

M_RWU EQU 6

; Receiver Wakeup Enable

M_WOMS EQU 7

; Wired-OR Mode Select

M_SCRE EQU 8

; SCI Receiver Enable

M_SCTE EQU 9

; SCI Transmitter Enable

M_ILIE EQU 10

; Idle Line Interrupt Enable

M_SCRIE EQU 11

; SCI Receive Interrupt Enable

M_SCTIE EQU 12

; SCI Transmit Interrupt Enable

M_TMIE EQU 13

; Timer Interrupt Enable

M_TIR EQU 14

; Timer Interrupt Rate

M_SCKP EQU 15

; SCI Clock Polarity

M_REIE EQU 16

; SCI Error Interrupt Enable (REIE)

;

SCI Status Register Bit Flags

M_TRNE EQU 0

; Transmitter Empty

M_TDRE EQU 1

; Transmit Data Register Empty

M_RDRF EQU 2

; Receive Data Register Full

M_IDLE EQU 3

; Idle Line Flag

M_OR EQU 4

; Overrun Error Flag

M_PE EQU 5

; Parity Error

M_FE EQU 6

; Framing Error Flag

M_R8 EQU 7

; Received Bit 8 (R8) Address

;

SCI Clock Control Register

M_CD EQU $FFF

; Clock Divider Mask (CD0-CD11)

M_COD EQU 12

; Clock Out Divider

M_SCP EQU 13

; Clock Prescaler

M_RCM EQU 14

; Receive Clock Mode Source Bit

M_TCM EQU 15

; Transmit Clock Source Bit

;------------------------------------------------------------------------

;

EQUATES for Synchronous Serial Interface (SSI)

;

;------------------------------------------------------------------------

;

M_TX00 EQU $FFFFBC

; SSI0 Transmit Data Register 0

M_TX01 EQU $FFFFBB

; SSIO Transmit Data Register 1

M_TX02 EQU $FFFFBA

; SSIO Transmit Data Register 2

M_TSR0 EQU $FFFFB9

; SSI0 Time Slot Register

M_RX0 EQU $FFFFB8

; SSI0 Receive Data Register

M_SSISR0 EQU $FFFFB7

; SSI0 Status Register

M_CRB0 EQU $FFFFB6

; SSI0 Control Register B

M_CRA0 EQU $FFFFB5

; SSI0 Control Register A

M_TSMA0 EQU $FFFFB4

; SSI0 Transmit Slot Mask Register A

M_TSMB0 EQU $FFFFB3

; SSI0 Transmit Slot Mask Register B

M_RSMA0 EQU $FFFFB2

; SSI0 Receive Slot Mask Register A

M_RSMB0 EQU $FFFFB1

; SSI0 Receive Slot Mask Register B

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

DSP56321 Datasheet(PDF) 75 Page - NXP Semiconductors

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