 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
RC32012A Datasheet(PDF) 1 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
RC32012A Datasheet(HTML) 1 Page - Renesas Technology Corp |
|
|
1 / 66 page  Datasheet R31DS0078EU0103 Rev.1.03 Page 1 Sep 15, 2022 © 2021-2022 Renesas Electronics The RC32012A is a fully integrated, low-power, high- performance jitter attenuator and clock generator. The device supports JEDEC JESD204B/C for converter synchronization and SyncE for network-based synchronization. The RC32012A is ideal for providing reference clocks for high-speed serial links up to 28Gbps Ethernet in modular switch line cards and fabric cards in data center equipment, and for clocking data converters in small cell wireless equipment. The device is a member of Renesas' high-performance FemtoClock family and radio clock family. Applications ▪ Switches / Routers ▪ Jitter attenuation for 10 / 25 / 40 / 100 / 200 / 400 Gbps Ethernet PHYs in Switch Line Cards ▪ Clock generation for 10 /25 / 40 / 100 / 200 / 400 Gbps Ethernet PHYs in Switch Fabric Cards ▪ Small Cell for 4.5G and 5G ▪ Medical Imaging ▪ Professional Audio and Video Product Options ▪ 10 × 10 × 0.9 mm 72-QFN package ▪ 12 differential or 24 single-ended outputs Features ▪ Can be configured as clock generator or jitter attenuator/synchronizer ▪ Low power, less than 1.2W typical ▪ Low jitter, less than 100 fs-RMS ▪ Compliant with ITU-T G.8262 and G.8262.1 option 1 and 2 for synchronous Ethernet Equipment Clock (EEC/eEEC) without degrading output jitter ▪ PCIe Gen 1-6 CC, SRIS and SRNS support ▪ Jitter attenuation with programmable loop bandwidth from 0.1Hz to 12kHz ▪ Up to four fractional output dividers and 12 integer output dividers • Each fractional output divider can be slaved with DPLL or SYS-DPLL or free-run locked to APLL ▪ DPLL can be configured as DCO and each fractional output divider can be configured as NCO or DCO ▪ Combo bus allows frequency sharing between DPLL, System DPLL, and each of the four fractional output dividers ▪ LVCMOS, LVPECL, LVDS, HCSL, CML, SSTL, HSTL output modes supported with programmable output swing and common mode voltage ▪ JESD204B/C support on differential or single ended outputs with DC-coupling or AC-coupling ▪ Up to seven single-ended or two differential clock inputs, one crystal/XO input, and one XO/TCXO/OCXO input ▪ Up to nine GPIO pins programmable to device select or system monitor options ▪ Supports 1MHz I2C, 400kHz SMBus, or 50MHz SPI serial port ▪ Internal non-volatile memory (up to 16 different configurations), or external serial I2C EEPROM provide default device settings on power-up. ▪ 2.5V and 3.3V core and 1.8V, 2.5V, and 3.3V output operation ▪ -40° to +85°C industrial temperature operation RC32012A FemtoClock Jitter Attenuator and Clock Generator |
Similar Part No. - RC32012A |
|
Similar Description - RC32012A |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
