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RC32012A Datasheet(PDF) 23 Page - Renesas Technology Corp

Part # RC32012A
Description  FemtoClock Jitter Attenuator and Clock Generator
PDF  66 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

RC32012A Datasheet(HTML) 23 Page - Renesas Technology Corp

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R31DS0078EU0103 Rev.1.03
Page 23
Sep 15, 2022
RC32012A Datasheet
tR / tF
Output
Rise and
Fall Times
20% to
80%
Differential
Output[15]
[16]
VDDO_Qx[17] = 3.3V ±5%,
2.5V±5% or 1.8V ±5%
SWING[18] = 00
100
400
ps
SWING = 01
100
450
SWING = 10
SWING = 11
LVCMOS
Output[19]
VDDO_Qx = 3.3V ±5%
TERM[20] = 00
100
254
380
ps
TERM = 01
100
262
400
TERM = 10
110
275
460
TERM = 11
115
268
510
VDDO_Qx = 2.5V ±5%
TERM = 00
115
285
405
ps
TERM = 01
120
293
470
TERM = 10
120
315
525
TERM = 11
140
347
565
VDDO_Qx = 1.8V ±5%
TERM = 00
205
417
590
ps
TERM = 01
205
458
715
TERM = 10
230
459
800
TERM = 11
235
482
880
VDDO_Qx = 1.5V ±5%[21]
TERM = 00
415
558
730
ps
TERM = 01
545
747
985
TERM = 10
615
890
1145
TERM = 11
690
1011
1305
VDDO_Qx = 1.2V ±5%[21]
TERM = 00
800
986
1250
ps
TERM = 01
1180
1416
1835
TERM = 10
1415
1715
2195
TERM = 11
1650
1980
2520
odc
Output
Duty Cycle
Differential
Output
PULSE = 50%
fOUT < 500MHz
47
50
53
%
500MHz ≤ fOUT <
800MHz
45
50
55
%
fOUT ≥ 800MHz
40
50
60
%
LVCMOS
PULSE = 50%
VDDO_Qx = 3.3V or
2.5V
47
50
53
%
VDDO_Qx = 1.8V or
1.5V
45
50
55
VDDO_Qx = 1.2V
42
50
58
tLOCK
1PPS Locking Time
17mHz loop bandwidth, phase and frequency snap
enabled
20
S
tSTARTUP
Start-up
Time[22]
Regulators
Ready[23]
3
s
Internal
OTP Start-
up
Synthesizer mode
7
10
ms
DPLL mode, with a loop bandwidth
setting of 300Hz[24]
1.5
s
Table 18. AC Characteristics[1][2] (Cont.)
Symbol
Parameter
Test Condition
Minimum
Typical
Maximum
Unit



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