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DSPIC30F Datasheet(PDF) 243 Page - Microchip Technology |
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DSPIC30F Datasheet(HTML) 243 Page - Microchip Technology |
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243 / 248 page  2004 Microchip Technology Inc. Preliminary DS70083G-page 241 dsPIC30F Operating Function Description ................................ 103 Operation During CPU Idle Mode ............................. 105 Operation During CPU Sleep Mode.......................... 105 SDOx Disable ........................................................... 103 Slave Select Synchronization ................................... 105 SPI1 Register Map.................................................... 106 SPI2 Register Map.................................................... 106 Timing Characteristics Master Mode (CKE = 0) .................................... 208 Master Mode (CKE = 1) .................................... 209 Slave Mode (CKE = 1) .............................. 210, 211 Timing Requirements Master Mode (CKE = 0) .................................... 208 Master Mode (CKE = 1) .................................... 209 Slave Mode (CKE = 0) ...................................... 210 Slave Mode (CKE = 1) ...................................... 212 Word and Byte Communication ................................ 103 Status Bits, Their Significance and the Initialization Condition for RCON Register, Case 1 ...................... 163 Status Bits, Their Significance and the Initialization Condition for RCON Register, Case 2 ...................... 164 Status Register ................................................................... 22 Z Status Bit ................................................................. 22 Symbols Used in Opcode Descriptions............................. 170 System Integration ............................................................ 153 Register Map............................................................. 168 T Table Instruction Operation Summary ................................ 63 Temperature and Voltage Specifications AC ............................................................................. 195 DC............................................................................. 184 Timer1 Module .................................................................... 81 16-bit Asynchronous Counter Mode ........................... 81 16-bit Synchronous Counter Mode ............................. 81 16-bit Timer Mode....................................................... 81 Gate Operation ........................................................... 82 Interrupt....................................................................... 82 Operation During Sleep Mode .................................... 82 Prescaler..................................................................... 82 Real-Time Clock ......................................................... 82 Interrupts............................................................. 83 Oscillator Operation ............................................ 83 Register Map............................................................... 84 Timer2 and Timer3 Selection Mode .................................. 100 Timer2/3 Module ................................................................. 85 16-bit Timer Mode....................................................... 85 32-bit Synchronous Counter Mode ............................. 85 32-bit Timer Mode....................................................... 85 ADC Event Trigger...................................................... 88 Gate Operation ........................................................... 88 Interrupt....................................................................... 88 Operation During Sleep Mode .................................... 88 Register Map............................................................... 89 Timer Prescaler........................................................... 88 Timer4/5 Module ................................................................. 91 Register Map............................................................... 93 Timing Characteristics A/D Conversion 10-Bit (ASAM = 0, SSRC = 000)....................... 220 Bandgap Start-up Time............................................. 200 CAN Module I/O........................................................ 217 CLKOUT and I/O....................................................... 198 DCI Module AC-Link Mode ................................................... 207 Multichannel, I2S Modes ................................... 205 External Clock .......................................................... 195 I2C Bus Data Master Mode..................................................... 213 Slave Mode ...................................................... 215 I2C Bus Start/Stop Bits Master Mode..................................................... 213 Slave Mode ...................................................... 215 Input Capture (CAPX)............................................... 203 OC/PWM Module...................................................... 204 Oscillator Start-up Timer........................................... 199 Output Compare Module .......................................... 203 Power-up Timer ........................................................ 199 Reset ........................................................................ 199 SPI Module Master Mode (CKE = 0).................................... 208 Master Mode (CKE = 1).................................... 209 Slave Mode (CKE = 0)...................................... 210 Slave Mode (CKE = 1)...................................... 211 Type A, B and C Timer External Clock..................... 201 Watchdog Timer ....................................................... 199 Timing Diagrams CAN Bit..................................................................... 128 Frame Sync, AC-Link Start of Frame ....................... 138 Frame Sync, Multi-Channel Mode ............................ 138 I2S Interface Frame Sync ......................................... 138 PWM Output ............................................................. 101 Time-out Sequence on Power-up (MCLR Not Tied to V DD), Case 1 ..................... 160 Time-out Sequence on Power-up (MCLR Not Tied to V DD), Case 2 ..................... 161 Time-out Sequence on Power-up (MCLR Tied to V DD) ......................................... 160 Timing Diagrams and Specifications DC Characteristics - Internal RC Accuracy .............. 197 Timing Diagrams.See Timing Characteristics Timing Requirements A/D Conversion 10-Bit ................................................................ 221 Bandgap Start-up Time ............................................ 200 Brown-out Reset....................................................... 200 CLKOUT and I/O ...................................................... 198 DCI Module AC-Link Mode................................................... 207 Multichannel, I2S Modes................................... 206 External Clock .......................................................... 196 I2C Bus Data (Master Mode) .................................... 214 I2C Bus Data (Slave Mode) ...................................... 216 Input Capture............................................................ 203 Oscillator Start-up Timer........................................... 200 Output Compare Module .......................................... 203 Power-up Timer ........................................................ 200 Reset ........................................................................ 200 Simple OC/PWM Mode ............................................ 204 SPI Module Master Mode (CKE = 0).................................... 208 Master Mode (CKE = 1).................................... 209 Slave Mode (CKE = 0)...................................... 210 Slave Mode (CKE = 1)...................................... 212 Type A Timer External Clock.................................... 201 Type B Timer External Clock.................................... 202 Type C Timer External Clock.................................... 202 Watchdog Timer ....................................................... 200 Timing Specifications PLL Clock ................................................................. 197 |
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