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DSPIC30F Datasheet(PDF) 241 Page - Microchip Technology |
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DSPIC30F Datasheet(HTML) 241 Page - Microchip Technology |
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241 / 248 page  2004 Microchip Technology Inc. Preliminary DS70083G-page 239 dsPIC30F F Fast Context Saving............................................................ 60 Flash Program Memory ...................................................... 63 Control Registers ........................................................ 64 NVMADR ............................................................ 64 NVMADRU.......................................................... 64 NVMCON ............................................................ 64 NVMKEY............................................................. 64 I I/O Pin Specifications Input .......................................................................... 191 Output ....................................................................... 192 I/O Ports .............................................................................. 75 Parallel (PIO) .............................................................. 75 I2C ..................................................................................... 107 I2C 10-bit Slave Mode Operation ...................................... 109 Reception.................................................................. 110 Transmission............................................................. 109 I2C 7-bit Slave Mode Operation ........................................ 109 Reception.................................................................. 109 Transmission............................................................. 109 I2C Master Mode Operation .............................................. 111 Baud Rate Generator................................................ 112 Clock Arbitration........................................................ 112 Multi-Master Communication, Bus Collision and Bus Arbitration ........................................... 112 Reception.................................................................. 111 Transmission............................................................. 111 I2C Master Mode Support ................................................. 111 I2C Module ........................................................................ 107 Addresses ................................................................. 109 Bus Data Timing Characteristics Master Mode ..................................................... 213 Slave Mode ....................................................... 215 Bus Data Timing Requirements Master Mode ..................................................... 214 Slave Mode ....................................................... 216 Bus Start/Stop Bits Timing Characteristics Master Mode ..................................................... 213 Slave Mode ....................................................... 215 General Call Address Support .................................. 111 Interrupts................................................................... 110 IPMI Support ............................................................. 111 Operating Function Description ................................ 107 Operation During CPU Sleep and Idle Modes .......... 112 Pin Configuration ...................................................... 107 Programmer’s Model................................................. 107 Register Map............................................................. 113 Registers................................................................... 107 Slope Control ............................................................ 111 Software Controlled Clock Stretching (STREN = 1).. 110 Various Modes .......................................................... 107 I2S Mode Operation .......................................................... 142 Data Justification....................................................... 142 Frame and Data Word Length Selection................... 142 Idle Current (I IDLE) ............................................................ 187 In-Circuit Serial Programming (ICSP) ......................... 63, 153 Input Capture (CAPX) Timing Characteristics .................. 203 Input Capture Module ......................................................... 95 Interrupts..................................................................... 97 Register Map............................................................... 98 Input Capture Operation During Sleep and Idle Modes ...... 97 CPU Idle Mode............................................................ 97 CPU Sleep Mode ........................................................ 97 Input Capture Timing Requirements................................. 203 Input Change Notification Module....................................... 79 Register Map (Bits 15-8)............................................. 79 Register Map (Bits 7-0)............................................... 79 Instruction Addressing Modes ............................................ 47 File Register Instructions ............................................ 48 Fundamental Modes Supported ................................. 47 MAC Instructions ........................................................ 48 MCU Instructions ........................................................ 48 Move and Accumulator Instructions ........................... 48 Other Instructions ....................................................... 48 Instruction Flow................................................................... 24 Pipeline 1-Word, 1-Cycle (Figure) .................................... 24 1-Word, 2-Cycle (Figure) .................................... 24 1-Word, 2-Cycle MOV.D Operations (Figure)..... 25 1-Word, 2-Cycle Table Operations (Figure) ....... 25 1-Word, 2-Cycle with Instruction Stall (Figure) ... 26 2-Word, 2-Cycle DO, DOW (Figure)................... 26 2-Word, 2-Cycle GOTO, CALL (Figure) ............. 25 Instruction Set Overview................................................................... 172 Summary .................................................................. 169 Instruction Stalls ................................................................. 49 Introduction................................................................. 49 Raw Dependency Detection ....................................... 49 Inter-Integrated Circuit. See I2C. Internal Clock Timing Examples ....................................... 197 Interrupt Controller Register Map .............................................................. 61 Interrupt Priority .................................................................. 56 Interrupt Sequence ............................................................. 59 Interrupt Stack Frame................................................. 59 Interrupts ............................................................................ 55 L Load Conditions................................................................ 195 Low Voltage Detect (LVD) ................................................ 165 Low-Voltage Detect Characteristics.................................. 192 LVDL Characteristics ........................................................ 193 M Memory Organization ......................................................... 17 Core Register Map ..................................................... 43 Modes of Operation Disable...................................................................... 125 Initialization............................................................... 125 Listen All Messages.................................................. 125 Listen Only................................................................ 125 Loopback .................................................................. 125 Normal Operation ..................................................... 125 Modulo Addressing ............................................................. 50 Applicability................................................................. 53 Decrementing Buffer Operation Example................... 52 Incrementing Buffer Operation Example .................... 51 Restrictions................................................................. 53 Start and End Address ............................................... 50 W Address Register Selection.................................... 51 MPLAB ASM30 Assembler, Linker, Librarian ................... 178 MPLAB ICD 2 In-Circuit Debugger ................................... 179 MPLAB ICE 2000 High Performance Universal In-Circuit Emulator.................................................... 179 MPLAB ICE 4000 High Performance Universal In-Circuit Emulator.................................................... 179 |
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