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DSPIC30F Datasheet(PDF) 244 Page - Microchip Technology |
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DSPIC30F Datasheet(HTML) 244 Page - Microchip Technology |
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244 / 248 page ![]() dsPIC30F DS70083G-page 242 Preliminary 2004 Microchip Technology Inc. Traps ................................................................................... 57 Hard and Soft .............................................................. 58 Sources ....................................................................... 57 Address Error Trap ............................................. 58 Math Error Trap................................................... 57 Oscillator Fail Trap.............................................. 58 Stack Error Trap.................................................. 58 U UART Module Address Detect Mode ............................................... 119 Auto Baud Support.................................................... 120 Baud Rate Generator ................................................ 119 Enabling and Setting Up ........................................... 117 Framing Error (FERR)............................................... 119 Idle Status ................................................................. 119 Loopback Mode ........................................................ 119 Operation During CPU Sleep and Idle Modes .......... 120 Overview ................................................................... 115 Parity Error (PERR) .................................................. 119 Receive Break........................................................... 119 Receive Buffer (UxRXB) ........................................... 118 Receive Buffer Overrun Error (OERR Bit) ................ 118 Receive Interrupt....................................................... 118 Receiving Data.......................................................... 118 Receiving in 8-bit or 9-bit Data Mode........................ 118 Reception Error Handling.......................................... 118 Transmit Break ......................................................... 118 Transmit Buffer (UxTXB) .......................................... 117 Transmit Interrupt ..................................................... 118 Transmitting Data ..................................................... 117 Transmitting in 8-bit Data Mode................................ 117 Transmitting in 9-bit Data Mode................................ 117 UART1 Register Map................................................ 121 UART2 Register Map................................................ 121 UART Operation Idle Mode .................................................................. 120 Sleep Mode .............................................................. 120 Unit ID Locations .............................................................. 153 Universal Asynchronous Receiver Transmitter. See UART. W Wake-up from Sleep ......................................................... 153 Wake-up from Sleep and Idle ............................................. 60 Watchdog Timer Timing Characteristics .............................................. 199 Timing Requirements................................................ 200 Watchdog Timer (WDT)............................................ 153, 165 Enabling and Disabling ............................................. 165 Operation .................................................................. 165 WWW, On-Line Support ..................................................... 16 |
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