ICS843156AK REVISION B May 26, 2016

14

©2016 Integrated Device Technology, Inc.

ICS843156 Data Sheet

CRYSTAL-TO-LVPECL CLOCK SYNTHESIZER

Power Considerations

This section provides information on power dissipation and junction temperature for the ICS843156.

Equations and example calculations are also provided.

1.

Power Dissipation.

The total power dissipation for the ICS843156 is the sum of the core power plus the power dissipation in the load(s).

The following is the power dissipation for VCCO = 3.3V + 5% = 3.465V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipation in the load.

•

Power (core)MAX = VCCO_MAX * IEE_MAX = 3.465V * 179mA = 620.235mW

•

Power (outputs)MAX = 30mW/Loaded Output pair

If all outputs are loaded, the total power is 10 * 30mW = 300mW

Total Power_MAX (3.3V, with all outputs switching) = 620.235mW + 300mW = 920.235mW

2. Junction Temperature.

unction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The

maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond

wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj =



JA * Pd_total + TA

Tj = Junction Temperature



JA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance



JA must be used. Assuming no air flow and

a multi-layer board, the appropriate value is 37°C/W per Table 7 below.

Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:

70°C + 0.920W * 37°C/W = 1046°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

Table 7. Thermal Resistance JA for 32 Lead VFQFN, Forced Convection



JA by Velocity

Meters per Second

01

2.5

Multi-Layer PCB, JEDEC Standard Test Boards

37.0°C/W

32.4°C/W

29.0°C/W