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7.6.1.6 Calibration Register (Address = 5h) [reset = 0000h]

The calibration register shown in Table 7-9 must be programmed to receive valid current and power results after

initial power up or power cycle events.

This register provides the device with the value of the shunt resistor that was present to create the measured

differential voltage. It also sets the resolution of the Current Register. Programming this register sets the

Current_LSB and the Power_LSB.

Table 7-9. Calibration Register Field Descriptions

Bit

Field

Type

Reset

Description

Reserved

14-0

SHUNT_CAL

R/W

0000h

Programmed value needed for doing the shunt voltage to current

conversion.

Return to the Summary Table.

7.6.1.7 Mask/Enable Register (Address = 6h) [reset = 0000h]

The Mask/Enable Register is shown in Table 7-10.

Table 7-10. Mask/Enable Register Field Descriptions

Bit

Field

Type

Reset

Description

SOL (Shunt Over-limit)

R/W

Setting this bit high configures the ALERT pin to be asserted if the shunt voltage

conversion result exceeds the value programmed in the LIMIT register

SUL (Shunt Under-limit)

R/W

Setting this bit high configures the ALERT pin to be asserted if the shunt voltage

conversion result is below the value programmed in the LIMIT register.

Cannot be set if Shunt overlimit is set.

BOL (Bus Over-limit)

R/W

Setting this bit high configures the ALERT pin to be asserted if the bus voltage

conversion result exceeds the value programmed in the LIMIT register

Cannot be set if Shunt overlimit or Shunt underlimit is set.

BUL (Bus Under-limit)

R/W

Setting this bit high configures the ALERT pin to be asserted if the bus voltage

conversion result is below the value programmed in the LIMIT register

Cannot be set if Shunt over limit, Shunt under limit or Bus over limit is set.

POL (Power Over-limit)

R/W

Setting this bit high configures the ALERT pin to be asserted if the power result

exceeds the value programmed in the LIMIT register

Cannot be set if Shunt over limit, Shunt under limit, Bus over limit or Bus under

limit is set.

CNVR (Conversion

Ready)

R/W

Setting this bit high configures the ALERT pin to be asserted when the

Conversion Ready Flag, Bit 3, is asserted indicating that the device is ready

for the next conversion.

0b = Disable conversion ready flag on ALERT pin

1b = Enables conversion ready flag on ALERT pin

9-6

Reserved

0000b

MemError

CRC or ECC error

AFF (Alert Function

Flag)

Alert Function Flag -While only one Alert Function can be monitored at the

ALERT pin at a time, the Conversion Ready can also be enabled to assert the

ALERT pin. Reading the Alert Function Flag following an alert allows the user to

determine if the Alert Function was the source of the Alert.

When the Alert Latch Enable bit is set to Latch mode, the Alert Function Flag bit

clears only when the Mask/Enable Register is read. When the Alert Latch Enable

bit is set to Transparent mode, the Alert Function Flag bit is cleared following the

next conversion that does not result in an Alert condition.

INA234

SBOS844C – MAY 2021 – REVISED MARCH 2023

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