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SN74HCS273 Datasheet(PDF) 9 Page - Texas Instruments

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Part # SN74HCS273
Description  SN74HCS273 Octal D-Type Flip-Flop with Schmitt-Trigger Inputs and Asynchronous Clear
PDF  27 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

SN74HCS273 Datasheet(HTML) 9 Page - Texas Instruments

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8 Detailed Description
8.1 Overview
The SN74HCS273 contains 8 positive-edge-triggered D-type flip-flops with shared direct active low clear (CLR)
input.
Information at the data (D) inputs meeting the setup time requirements is transferred to the (Q) outputs on the
positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not
related directly to the transition time of the positive-going pulse. When CLK is at either the high or low level or
transitioning from a high level to a low level, the D input has no effect at the output.
Information at the data (Q) outputs can be asychronously cleared with a low level input through the clear (CLR)
pin.
8.2 Functional Block Diagram
One of Eight Channels
Shared Control Inputs
One of Eight D-Type Flip-Flops
CLK
C
C
xD
CLR
C
C
C
C
C
C
C
C
xQ
R
R
8.3 Feature Description
8.3.1 Balanced CMOS Push-Pull Outputs
This device includes balanced CMOS push-pull outputs. The term balanced indicates that the device can sink
and source similar currents. The drive capability of this device may create fast edges into light loads, so routing
and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable
of driving larger currents than the device can sustain without being damaged. It is important for the output power
of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the
Absolute Maximum Ratings must be followed at all times.
Unused push-pull CMOS outputs should be left disconnected.
8.3.2 CMOS Schmitt-Trigger Inputs
This device includes inputs with the Schmitt-trigger architecture. These inputs are high impedance and are
typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics table
from the input to ground. The worst case resistance is calculated with the maximum input voltage, given in the
Absolute Maximum Ratings table, and the maximum input leakage current, given in the Electrical Characteristics
table, using Ohm's law (R = V ÷ I).
www.ti.com
SN74HCS273
SCLS851D – MARCH 2021 – REVISED JANUARY 2023
Copyright © 2023 Texas Instruments Incorporated
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