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SN74HCS273 Datasheet(PDF) 14 Page - Texas Instruments

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Part # SN74HCS273
Description  SN74HCS273 Octal D-Type Flip-Flop with Schmitt-Trigger Inputs and Asynchronous Clear
PDF  27 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

SN74HCS273 Datasheet(HTML) 14 Page - Texas Instruments

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10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in the
following layout example.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices, inputs must never be left floating. In many cases,
functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
11.2 Layout Example
1
2
3
4
5
6
7
20
19
18
17
16
15
14
GND
VCC
0.1
F
Bypass capacitor
placed close to the
device
Avoid 90°
corners for
signal lines
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
Unused input
tied to GND
8
13
9
12
10
11
CLR
1Q
1D
2D
2Q
3Q
3D
4D
4Q
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
Unused output
left floating
GND
Figure 11-1. Example Layout for the SN74HCS273
PW Package
F
Bypass capacitor
placed close to the
device
Avoid 90°
corners for
signal lines
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
Unused input
tied to GND
VCC
CLK
Unused output
left floating
GND
1Q
1D
2D
2Q
3Q
3D
4D
4Q
CLR
8Q
8D
7D
7Q
6Q
6D
5D
5Q
1
20
10
11
2
3
4
5
6
7
8
9
12
13
14
15
16
17
18
19
GND
V
CC
GND
Figure 11-2. Example Layout for the SN74HCS273
RKS Package
SN74HCS273
SCLS851D – MARCH 2021 – REVISED JANUARY 2023
www.ti.com
14
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Product Folder Links: SN74HCS273



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