MPC9330 REVISION 8 3/11/16

9

©2016 Integrated Device Technology, Inc.

MPC9330 Data Sheet

3.3V, 1:6, LVCMOS PLL CLOCK GENERATOR

VL =VS ( Z0  (RS+R0 + Z0))

Z0 = 50  || 50 

RS = 36  || 36 

R0 = 14 

VL = 3.0 (25  (18+14+25)

= 1.31 V

At the load end, the voltage will double due to the near unity

reflection coefficient, to 2.6 V. It will then increment towards the

quiescent 3.0 V in steps separated by one round trip delay (in this

case 4.0 ns).

Final skew data pending specification.

Figure 5. Single versus Dual Waveforms

Since this step is well above the threshold region, it will not cause

any false clock triggering; however, designers may be

uncomfortable with unwanted reflections on the line. To better match

the impedances when driving multiple lines, the situation in Figure 6

should be used. In this case the series terminating resistors are

reduced such that when the parallel combination is added to the

output buffer impedance, the line impedance is perfectly matched.

Figure 6. Optimized Dual Line Termination

Figure 7. CCLK MPC9330 AC Test Reference for Vcc = 3.3 V

Time (ns)

3.0

2.5

2.0

1.5

1.0

0.5

0

2

4

6

8

10

12

14

OutB

tD = 3.9386

OutA

tD = 3.8956

In

14

 + 22  || 22  = 50 || 50 

25

 = 25 

14



MPC9330

Output

Buffer

RS = 22 

ZO = 50 

RS = 22 

ZO = 50 

Pulse

Generator

Z = 50



RT = 50 

ZO = 50 

RT = 50 

ZO = 50 

MPC9930 DUT

VTT

VTT