MPC9330 REVISION 8 3/11/16

2

©2016 Integrated Device Technology, Inc.

MPC9330 Data Sheet

3.3V, 1:6, LVCMOS PLL CLOCK GENERATOR

Figure 1. MPC9330 Logic Diagram

Figure 2. MPC9330 32-Lead Package Pinout (Top View)

PWR_DN

FB_SEL

FB_IN

REF_SEL

CCLK

XTAL_IN

FSELC

FSELA

PLL_EN

PLL

1

0

2

4

6

1

0

0

1

16

1

0

1

0

2

4

1

0

1

0

3

OE/MR

QA0

QA1

QB0

QB1

QC0

QC1

Bank A

Bank B

Bank C

25k

25k

3 x 25k

25k

VCC

VCC

25k

VCC

25k

VCC

3 x 25k

VCC

CLK

Stop

CLK

Stop

CLK

Stop

Ref

FB

VCO

CLK_STOP1

CLK_STOP0

FSELB

XTAL_OUT

XTAL

25k

Power_On Reset

GND

QA1

QA0

VCC

FSELA

FSELB

FSELC

GND

QC1

QC0

VCC

FB_IN

CLK_STOP1

25

26

27

28

29

30

31

32

15

14

13

12

11

10

9

12

3

4

5

6

78

24

23

22

21

20

19

18

17

16

MPC9330

NC

CLK_STOP0

NC

It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Please see Applications Information section for details.