AND8020 datasheet(8/18 Pages) AD

8 / 18 page

AND8020/D

http://onsemi.com

Internal 100

W Termination (LVDS)

For some technologies, such as LVDS, this passive 100

internal termination can provide sufficient termination for the

driver as shown in Figure 10. Devices with a Combo Pin will

require this pin to remain open, while devices with singulated

internal resistors require the two pinned out Vt nodes for a

differential pair to be shorted together to provide the 100

termination.

Figure 10. LVDS Interconnect with Internal

Termination

Open Vt Pin

(*or twisted pair)

LVDS Driver

Receiver

*T−Line Z0

Internal Termination Combo Pin

Internal Termination Singulated Pins

(*or twisted pair)

LVDS Driver

Receiver

*T−Line Z0

Vt1

Vt2

Shorted

Differential ECL outputs can be terminated as independent

complimentary single−ended lines. Both sides of any

differential pair must be terminated as identically as possible

to minimize phase error and pulse width duty cycle skew.

The IOH currents in these two cases will vary the DC VOH

levels by

$40 mV. However in the vast majority of cases, DC

levels are well centered in their specification windows, thus

this variation will simply move the level within the valid

specification window and no loss of worst case noise margin

will be seen.

The IOL situation on the other hand does pose a potential

AC problem. In the worst Case #1 IOLmin situation, the

output emitter follower could move into the cutoff state

(0 mA). The output emitter followers of ECL devices are

designed to be in the conducting, active region of operation

at all times. When forced into cutoff, the delay of the device

will be increased due to the extra time required to pull the

output emitter follower out of the cutoff state. Again, this

situation will arise only under a number of simultaneous

worst case situations and therefore, is highly unlikely to

occur. But, because of the potential, it should not be

overlooked.

Output Drive Characteristics

Figure 11 shows the nominal output characteristics for

ECL devices operating in negative ECL mode, driving

various load impedances (including the standard 50

returned to a negative two volt supply. The output

resistances, RH (high state output resistance) and RL (low

state output resistance), are obtained from the reciprocal of

the slope at the desired operating point. Many applications

require loads other than 50

W − the resulting VOH and VOL

levels can be estimated using the following technique.

VOH

−2.0

−5

−10

−15

−0.75

−1.0

−1.25

−20

−25

−30

−35

−40

−1.75

−0.5 −0.25

OUTPUT VOLTAGE (V)

SLOPE = 6

W − 8 W

−1.5

Figure 11. Normal Output Levels Driving Various

Load Impedances

VOL

TA =25°C

to − 2.0 V

150

to − 2.0 V

100

to − 2.0 V

AND8020 Datasheet(PDF) 8 Page - Analog Devices

AND8020 Datasheet(HTML) 8 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Datasheet Download

Link URL