AND8020 datasheet(17/18 Pages) AD

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AND8020/D

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When the coupling capacitor is physically located near

enough to the receiver input pins to prohibit reflections on the

connecting trace length or signal impedance matching has

been accomplished prior to cap coupling, then a simple high

value resistor divider network from VCC to VEE is

recommended as shown in Figure 23. Differential and

Single−Ended AC Configurations Using Non−VBB Biasing

(A and B). This network total resistance may be from 1 K

to 10 K

W. For 50 W impedance traces, the typical value for the

voltage divider resistors are given in Table F. Typical Rebias

and Impedance Matching Resistor Network Values @

Z0 = 50. Note the impedance presented to a signal is

u5 KW.

Table F. Typical Rebias and Impedance Matching Resistor Network Values @ Z0 = 50

Resistor

|VCC−VEE| = 5.0 V

|VCC−VEE| = 3.3 V

|VCC−VEE| = 2.5 V

Units

R1 (R1

′)

R2 (R2

′)

Vrebias

3.3

2.2

1.7

When the coupling capacitor is physically located at a

distance from receiver over a trace or cable length capable

of sustaining reflections, a Thevenin parallel network

matching the line of impedance is recommended for their

suppression. This is shown in Figure 23. Differential and

Single−Ended AC Configurations Using Non−VBB Biasing

(A and B). The rebias voltage may always be safely set at

VCC−1.3. For 50

W impedance traces, the typical value for

the voltage divider resistors are given in Table G. Typical

Rebias and Impedance Matching Resistor Network Values @

Z0 = 50.

Table G. Typical Rebias and Impedance Matching Resistor Network Values @ Z0 = 50

Resistor

|VCC−VEE| = 5.0 V

|VCC−VEE| = 3.3 V

|VCC−VEE| = 2.5 V

Units

R1 (R1

′)

96.15

R2 (R2

′)

192

127

104.16

Vrebias

3.7

2.0

1.2

Figure 23. Differential and Single−Ended AC

Configurations Using Non−VBB Biasing

VCC

Receiver

OUT

OUTb

INb

VTT

0.001

VEE

VCC

Receiver

OUT

OUTb

VTT

0.001

VEE

A. Differential

B. Single−Ended

The characterized VBB reference voltage bias, VBIAS, is

VCC − 1.33 V, but a device is not restricted to this VBIAS

value. The VBIAS range is determined by the Vpp

amplitude and the signal HIGH level, VIH. Input HIGH

level, VIH, is constrained by the data sheet specification of

common mode range, VIHCMR or VCMR. Thus, the VBIAS

range is constrained:

VBIAS max + VIHCMRmax * (0.5 )(Vpp )

VBIAS min + VIHCMRmin * (0.5 )(Vpp )

A single−ended source into a differential type input signal

amplitude swing, Vpp, is typically constrained from

Vppmin = 300 mV to Vppmax = 1000 mV.

An input signal must swing symmetrically above and

below VBIAS to preserve a 50% duty cycle out of the

receiver. Differential signals must have identical crosspoint

voltages to preserve minimum phase error and duty cycle

error. Crosspoint voltages are determined by the matched

precision of the resistor divider network from VCC to VEE.

Auto−Oscillation Suppression without VBB

For a configuration without a VBB reference pin, such as

illustrated in Figure 23, the resistor network may be

modified to have an input voltage

D of 20 to 30 mV offset

between the input pins. Either a high resistor value divider

or a Thevenin parallel network may be modified to

accomplish this input voltage

D. This is accomplished by

altering the values of R1, R1

′, R2, and R2′.

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