AND8020/D

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2

INTRODUCTION

Static DC Termination Analysis

A standard Emitter Coupled Logic (ECL) output driver

typically uses a current switching differential with an emitter

follower for level shifting the output and the internal CML

levels to familiar ECL levels. This output driver architecture

presents about 6−8

W internal impedance in both LOW and

HIGH states when properly current biased. This results in a

each line) swinging around a DC voltage point of

correctly as shown in Figure 1.

Q

D

Driver

Receiver

8

W Internal Output

Impedance

Figure 1. Typical ECL Output with Emitter Follower Output Structure,

Typical Termination, and Typical ECL Input Interconnect

Q

D

For proper static and dynamic operation, the output

emitter follower transistor must remain in the active region

of operation which requires an external resistive path be

provided from the output pin to a voltage more negative than

a current bias for the Emitter Follower output structure.

When properly terminated and current biased (loaded),

the outputs will generate both: (1) static state voltage levels

edge (tr or tf) between state levels.

Static State Voltage Levels

Figure 2 illustrates the typical relationship of static signal

levels and dynamic transition edges between an Output

Driver Signal and a Receiver Input Signal. Both outputs of

a differential driver should always be terminated and loaded

as identically as possible to preserve minimum skew and

jitter operation of the device.

and Dynamic Transitions at Q or Q and D or D

tr

tf

tr

tf

Output

Driver

Signal

Input

Receiver

Signal