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AND8020 Datasheet(PDF) 9 Page - Analog Devices

Part # AND8020
Description  Termination of ECL Logic Devices with EF (Emitter Follower) OUTPUT Structure
PDF  18 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AND8020 Datasheet(HTML) 9 Page - Analog Devices

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AND8020/D
http://onsemi.com
9
SECTION 3. THEVENIN EQUIVALENT PARALLEL TERMINATION
R
R
R
R
Although the single resistor termination to VTT conserves
power, it requires an additional supply voltage. An alternate
approach to using a VTT power supply is to use a resistor
divider network as shown in Figure 12 to develop a
Thevenin voltage, VTT, and provide a parallel impedance
matching
AC
termination,
the
Thevenin
parallel
termination.
Figure 12. Thevenin Equivalent Parallel Termination
VEE
T−Line Z0
Driver
R2
R1
VCC
Receiver
R2
R2
R1
R1
Driver
Receiver
T−Line Z0
T−Line Z0
VEE
VCC
or Twisted Pair
VTT + VCC * 2.0V
+ VCC
R2
R1
) R2
*
*
*
*
*
*
*
(eq. 13)
Differential ECL outputs can be terminated as independent
complimentary single−ended lines. Both sides of a
differential pair must be terminated. Balanced, symmetrical
loading of each line must be preserved.
While a Thevenin Parallel technique dissipates more
termination power, it does not require the additional VTT
supply. This additional power is consumed entirely in the
external resistor divider network and thus will not change
the current being sourced by the device, hence it does not
alter the IC reliability or lifetime. As with standard parallel
termination, variance of VTT and VCC supplies must be
considered.
The Thevenin equivalent of the two resistors needs to be
equal to the characteristic impedance of the signal
transmission line. Calculated values for resistors R1 and R2
may be obtained from the following relationships.
R2
+ Z0
VCC * VEE
VCC * VTT
(eq. 14)
R1
+ R2
VCC * VTT
VTT
* VEE
(eq. 15)
Where:
VTT =VCC − 2.0 V
Z0 = Characteristic Impedance of the Signal
Transmission Line
For a typical VCC = 5.0 V PECL scheme, where VEE =
GND, VTT = 3.0 V, and Z0 = 50
W:
R2
+ 50 5 * 0
5
* 3 +
125
W
(eq. 16)
R1
+ 125 5 * 3
3
* 0 +
83.3
W
(eq. 17)
and cross−checking for VTT:
VTT + 5
125
125
) 83.3 +
3.0 V
(eq. 18)
VTT + VCC * 2.0 V + 3.0 V
(eq. 19)
For the typical VCC = 3.3 V LVPECL scheme, where
VEE = GND, VTT = 1.3 V, and Z0 = 50
W:
R2
+ 50
3.3
* 0
3.3
* 1.3 +
82.5
W
(eq. 20)
R1
+ 82.5 3.3 * 1.3
1.3
* 0
+ 126 W
(eq. 21)
and cross−checking for VTT:
VTT + 3.3
82.5
126
) 82.5 +
1.3 V
(eq. 22)
VTT + VCC * 2.0 V + 1.3 V
(eq. 23)
Table D. Thevenin Term Table
|VCC−VEE| = 5.0 V
|VCC−VEE| = 3.3 V
|VCC−VEE| = 2.5 V
Z0
R1
R2
Z0
R1
R2
Z0
R1
R2
50
83
125
50
127
83
50
250
62.5
70
117
175
70
178
115
70
350
87.5
75
125
188
75
190
123
75
375
93.8
80
133
200
80
203
132
80
400
100
90
150
225
90
229
149
90
450
112.5
100
167
250
100
253
165
100
500
125.5
120
200
300
120
305
198
120
600
150
150
250
375
150
381
248
150
750
187.5



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