ZAMC4100 datasheet(115/156 Pages) RENESAS

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ZAMC4100 Datasheet

115

January 26, 2016

4.8.3.

SPI Data Transfer Process

To start a transfer, the SPI SLAVE module must be enabled by setting the SPIEN bit in the Z1_SPICFG register

(Table 4.21) and then setting the clock period via the CDIV bit field in the Z1_SPICLKCFG register (Table 4.23).

The software then sets the SSN bit low, which enables the SPI SLAVE within the SBC. In addition, any necessary

interrupt source must be enabled. Note that the TX buffer (TxBUF) illustrated in Figure 4.5 is empty until the data

transfer has been started.

Upon expiration of the specified SSN set-up time period (see Table 1.16), the first byte to be transmitted is set up

by writing a data byte into the SPIDATA register. This will clear the TXEMPTY flag bit in the Z1_SPISTAT register

(Table 4.24). In the next system clock cycle, this byte is transferred into the shift register and this causes the

TXEMPTY and BUSY flag bits to be set in the Z1_SPISTAT register. This allows the user to place a second byte

into the TX buffer. The first byte is shifted out on the MOSI line and the SPI clock is generated.

Simultaneously, the MISO line is sampled and shifted in. Normally, the MISO line is sampled in the middle of a

transmitted bit. While the MOSI line changes its value at the same time as the SPI clock, there is a delay

regarding the MISO line as first the clock must be driven out of the chip into the connected SLAVE and then the

data must be driven back from the connected SLAVE. To relax the timing, especially for fast SPI clocks, the RX

data can be sampled at the end of a transmitted bit if configured via the SAMPLEPOS bit in the Z1_SPICFG

When the complete byte has been shifted in and the RX buffer is empty, the byte is stored into the RX buffer at

the byte boundary and the RXFULL flag bit is set in the Z1_SPICFG register, signaling the end of the byte

transfer.

If the RX buffer is already full and the byte inside the RX buffer is not read in the same cycle, the byte currently

received is rejected (lost) and the RXOF flag bit is set in the Z1_SPISTAT register (Table 4.24).

Note: Because the SPI module operates in a full-duplex mode, a dummy byte must be placed into the TX buffer if

a byte must be read from the SLAVE without any WRITE to the SLAVE.

4.8.4.

Continuous SPI Data Streaming

When a new byte is written into TX buffer before the end of an active byte transfer, the transfer of the new byte

starts immediately after the actual transfer. This means that the BUSY flag bit in the Z1_SPISTAT register stays

active at the end of the first transmitted byte.

4.8.5.

Abrupt SPI Discontinuity

Since it can be possible that the software disables the SPI while a transfer is in progress (not recommended), a

byte could be present in the TX buffer indicated by a low value of the TXEMPTY flag bit in the Z1_SPISTAT

4.8.6.

Interrupts and Status Flags in the Z1_SPISTAT Register

There are five status flags available in the Z1_SPISTAT register. Only four of them can be enabled to drive the

interrupt lines as summarized below and in Table 4.24. The software is required to deal with interrupt events for

proper SPI operation. The BUSY flag is used to reflect the operation state of the SPI module.

ZAMC4100 Datasheet(PDF) 115 Page - Renesas Technology Corp