PowerPC 604 RISC Microprocessor Technical Summary

15

NOTE

A bar over a signal name indicates that the signal is active low—for

example, ARTRY (address retry) and TS (transfer start). Active-low

signals are referred to as asserted (active) when they are low and negated

when they are high. Signals that are not active-low, such as AP0–AP3

(address bus parity signals) and TT0–TT4 (transfer type signals) are

referred to as asserted when they are high and negated when they are low.

1.2.5.3 Signal Configuration

Figure 5 illustrates the logical pin configuration of the 604, showing how the signals are grouped.

1.2.6 Clocking

The 604 has a phase-locked loop (PLL) that generates the internal processor clock. The input, or reference

signal, to the PLL is the bus clock. The feedback in the PLL guarantees that the processor clock is phase

locked to the bus clock, regardless of process variations, temperature changes, or parasitic capacitances. The

PLL also ensures a 50% duty cycle for the processor clock.

The 604 supports the following processor-to-bus clock frequency ratios—1:1, 1.5:1, 2:1, and 3:1, although

not all ratios are available for all frequencies. Table 1 shows the supported processor frequencies for

different bus frequencies.

Table 1. Supported Processor/Bus Frequency Ratios

Bus

Frequency

(MHz)

Supported Processor/Bus Clock Ratios

1:1

1.5:1

2:1

3:1

16.5–33.3

Yes

Yes

Yes

Yes

33.4–50.0

Yes

Yes

Yes

No

50.1–66.6

Yes

Yes

No

No

Freescale Semiconductor, Inc.

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