PowerPC 604 RISC Microprocessor Technical Summary

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at an address (exception vector) predetermined for each exception and the processor changes to supervisor

mode.

Although multiple exception conditions can map to a single exception vector, a more specific condition may

be determined by examining a register associated with the exception—for example, the DSISR and the

FPSCR. Additionally, specific exception conditions can be explicitly enabled or disabled by software.

The PowerPC architecture requires that exceptions be handled in program order; therefore, although a

particular PowerPC processor may recognize exception conditions out of order, exceptions are handled

strictly in order. When an instruction-caused exception is recognized, any unexecuted instructions that

appear earlier in the instruction stream, including any that have not yet entered the execute state, are

required to complete before the exception is taken. Any exceptions caused by those instructions must be

handled first. Likewise, exceptions that are asynchronous and precise are recognized when they occur

(unless they are masked), but the processor gradually powered down, and the reorder buffer is drained. The

address of the next sequential instruction is saved in SRR0 so execution can resume in the correct context

when the exception handler returns control to the interrupted process.

Unless a catastrophic condition causes a system reset or machine check exception, only one exception is

handled at a time. If, for example, a single instruction encounters multiple exception conditions, those

conditions are encountered sequentially. After the exception handler handles an exception, the instruction

execution continues until the next exception condition is encountered. This method of recognizing and

handling exception conditions sequentially guarantees that exceptions are recoverable.

Exception handlers should save the information stored in SRR0 and SRR1 early to prevent the program state

from being lost due to a system reset or machine check exception or to an instruction-caused exception in

the exception handler.

The PowerPC architecture supports four types of exceptions:

•

Synchronous, precise—These are caused by instructions. All instruction-caused exceptions are

handled precisely; that is, the machine state at the time the exception occurs is known and can be

completely restored.

•

Synchronous, imprecise—The PowerPC architecture defines two imprecise floating-point

exception modes, recoverable and nonrecoverable. The 604 implements only the imprecise

nonrecoverable mode. The imprecise, recoverable mode is treated as the precise mode in the 604.

•

Asynchronous—The OEA portion of the PowerPC architecture defines two types of asynchronous

exceptions:

— Asynchronous, maskable—The PowerPC architecture defines the external interrupt and

decrementer interrupt which are maskable and asynchronous exceptions. In the 604, and in

many PowerPC processors, the hardware interrupt is generated by the assertion of the Interrupt

(INT) signal, which is not defined by the architecture. In addition, the 604 implements one

additional interrupt, the system management interrupt, which performs similarly to the external

interrupt, and is generated by the assertion of the System Management Interrupt (SMI) signal.

When these exceptions occur, their handling is postponed until all instructions, and any

exceptions associated with those instructions, complete execution.

— Asynchronous, nonmaskable—There are two nonmaskable asynchronous exceptions that are

imprecise: system reset and machine check exceptions. Note that the OEA portion of the

PowerPC architecture, which defines how these exceptions work, does not define the causes or

the signals used to cause these exceptions. These exceptions may not be recoverable, or may

provide a limited degree of recoverability for diagnostic purpose.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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