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PowerPC 604 RISC Microprocessor Technical Summary

The PowerPC architecture defines two bits in the machine state register (MSR)—FE0 and FE1—that

determine how floating-point exceptions are handled. There are four combinations of bit settings, of which

the 604 implements three. These are as follows:

•

Ignore exceptions mode (FE0 = FE1 = 0). In this mode, the instruction dispatch logic feeds the FPU

as fast as possible and the FPU uses an internal pipeline to allow overlapped execution of

instructions. In this mode, floating-point exception conditions return a predefined value instead of

causing an exception.

•

Precise interrupt mode (FE0 = 1; FE1 = x). This mode includes both the precise mode and imprecise

recoverable mode defined in the PowerPC architecture. In this mode, a floating-point instruction

that causes a floating-point exception brings the machine to a precise state. In doing so, the 604

takes floating-point exceptions as defined by the PowerPC architecture.

•

Imprecise nonrecoverable mode (FE0 = 0; FE1 = 1). In this mode, when a floating-point instruction

causes a floating point exception, the save restore register 0 (SRR0) may point to an instruction

following the instruction that caused the exception.

The 604 exception classes are shown in Table 2.

The 604’s exceptions, and conditions that cause them, are listed in Table 3.

Table 2. Exception Classifications

Type

Exception

Asynchronous/nonmaskable

Machine check

System reset

Asynchronous/maskable

External interrupt

Decrementer

System management interrupt (not defined by the PowerPC architecture)

Synchronous/precise

Instruction-caused exceptions

Synchronous/imprecise

Floating-point exceptions (imprecise nonrecoverable mode)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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