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PowerPC 604 RISC Microprocessor Technical Summary

The 604 is a high-performance, superscalar PowerPC implementation of the PowerPC architecture. Like

other PowerPC processors, it adheres to the PowerPC architecture specifications but also has additional

features not defined by the architecture. These features do not affect software compatibility. The PowerPC

architecture allows optimizing compilers to schedule instructions to maximize performance through

efficient use of the PowerPC instruction set and register model. The multiple, independent execution units

in the 604 allow compilers to maximize parallelism and instruction throughput. Compilers that take

advantage of the flexibility of the PowerPC architecture can additionally optimize instruction processing of

the PowerPC processors.

1.3.2 Registers and Programming Model

The PowerPC architecture defines register-to-register operations for most computational instructions.

Source operands for these instructions are accessed from the registers or are provided as immediate values

embedded in the instruction opcode. The three-register instruction format allows specification of a target

register distinct from the two source operands. Load and store instructions transfer data between registers

and memory.

During normal execution, a program can access the registers, shown in Figure 6, depending on the

program’s access privilege (supervisor or user, determined by the privilege-level (PR) bit in the machine

state register (MSR)). Note that registers such as the general-purpose registers (GPRs) and floating-point

registers (FPRs) are accessed through operands that are part of the instructions. Access to registers can be

explicit (that is, through the use of specific instructions for that purpose such as Move to Special-Purpose

Register (mtspr) and Move from Special-Purpose Register (mfspr) instructions) or implicitly as the part of

the execution of an instruction. Some registers are accessed both explicitly and implicitly.

The numbers to the left of the SPRs indicate the number that is used in the syntax of the instruction operands

to access the register.

Figure 6 shows the registers implemented in the 604, indicating those that are defined by the PowerPC

architecture and those that are 604-specific. Note that these are all of these registers except the FPRs are 32-

bits wide.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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