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PowerPC 604e RISC Microprocessor Technical Summary

— Three-stage floating-point unit (FPU)

– Fully IEEE 754-1985-compliant FPU for both single- and double-precision operations

– Supports non-IEEE mode for time-critical operations

– Fully pipelined, single-pass double-precision design

– Hardware support for denormalized numbers

– Two-entry reservation station to minimize stalls

– Thirty-two 64-bit FPRs for single- or double-precision operands

— Load/store unit (LSU)

– Two-entry reservation station to minimize stalls

– Single-cycle, pipelined cache access

– Dedicated adder performs EA calculations

– Performs alignment and precision conversion for floating-point data

– Performs alignment and sign extension for integer data

– Four-entry finish load queue (FLQ) provides load miss buffering

– Six-entry store queue

– Supports both big- and little-endian modes

•

Rename buffers

— Twelve GPR rename buffers

— Eight FPR rename buffers

— Eight condition register (CR) rename buffers

The 604e rename buffers are described in Section 1.2.7, “Rename Buffers.”

•

Completion unit

— The completion unit retires an instruction from the 16-entry reorder buffer when all instructions

ahead of it have been completed and the instruction has finished execution.

— Guarantees sequential programming model (precise exception model)

— Monitors all dispatched instructions and retires them in order

— Tracks unresolved branches and flushes executed, dispatched, and fetched instructions if branch

is mispredicted

— Retires as many as four instructions per clock

•

Separate on-chip instruction and data caches (Harvard architecture)

— 32-Kbyte, four-way set-associative instruction and data caches

— LRU replacement algorithm

— 32-byte (eight-word) cache block size

— Physically indexed/physical tags. (Note that the PowerPC architecture refers to physical

address space as real address space.)

— Cache write-back or write-through operation programmable on a per page or per block basis

— Instruction cache can provide four instructions per clock; data cache can provide two words per

clock

— Caches can be disabled in software

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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