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PowerPC 604e RISC Microprocessor Technical Summary

•

Performance monitor can be used to help in debugging system designs and improving software

efficiency, especially in multiprocessor systems.

•

In-system testability and debugging features through JTAG boundary-scan capability

1.2 PowerPC 604e Microprocessor Hardware

Implementation

This section provides an overview of the 604e’s hardware implementation, including descriptions of the

functional units, shown in Figure 2, the cache implementation, MMU, and the system interface.

Note that Figure 2 provides a more detailed block diagram than that presented in Figure 1—showing the

additional data paths that contribute to the improved efficiency in instruction execution and more clearly

shows the relationships between execution units and their associated register files.

Figure 2. Block Diagram—Internal Data Paths

Fetch Unit

Branch

(Four-instruction

Dispatch Unit

BPU

32-Kbyte data cache

4-way, 8 words/block

Completion

Unit

Instruction dispatch buses

Result status buses

correction

LSU

MCIU

SCIU

SCIU

FPU

Result buses

Operand buses

dispatch)

RS(2)

RS(1)

RS(2)

RS(2)

RS(2)

CRU

RS(2)

RS(2)

GPR operand buses

GPR result buses

CR result bus

FPR operand buses

FPR result buses

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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