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PowerPC 604e RISC Microprocessor Technical Summary

1.2.8.2 Floating-Point Unit (FPU)

The FPU, shown in Figure 1 and Figure 2, is a single-pass, double-precision execution unit; that is, most

single- and double-precision operations require only a single pass, with a latency of three cycles.

As the decode/dispatch unit issues instructions to the FPU’s two reservation stations, source operand data

may be accessed from the FPRs, the floating-point rename buffers, or the result buses. Results in turn are

written to the floating-point rename buffers and to the reservation stations and are made available to

subsequent instructions. Instructions are executed from the reservation station in dispatch order.

1.2.8.3 Load/Store Unit (LSU)

The LSU, shown in Figure 1 and Figure 2, transfers data between the data cache and the result buses, which

route data to other execution units. The LSU supports the address generation and handles any alignment for

transfers to and from system memory. Note that the 604e provides additional hardware support for

misaligned little-endian accesses over previous versions of the 604. In the 604e, the conditions that cause

an alignment exception to be taken are the same regardless of whether the processor is in big- or little-endian

mode. When two accesses are required, the lower addressed word (in the current addressing mode) is

accessed first.

The LSU also supports cache control instructions and load/store multiple/string instructions. As noted

above, load and store instructions that update the base address register pass their results on the MCIU’s

result bus. This is the only exception to the dedicated use of result buses.

The LSU includes a 32-bit adder dedicated for EA calculation. Data alignment logic manipulates data to

support aligned or misaligned transfers with the data cache. The LSU’s load and store queues are used to

buffer instructions that have been executed and are waiting to be completed. The queues are used to monitor

data dependencies generated by data forwarding and out-of-order instruction execution ensuring a

sequential model.

The LSU allows load operations to precede pending store operations and resolves any dependencies

incurred when a pending store is to the same address as the load. If such a dependency exists, the LSU delays

the load operation until the correct data can be forwarded. If only the low-order 12 bits of the EAs match,

both addresses may be aliases for the same physical address, in which case, the load operation is delayed

until the store has been written back to the cache, ensuring that the load operation retrieves the correct data.

The LSU does not allow the following operations to be performed on unresolved branches:

•

Store operations

•

Loading of noncacheable data or cache miss operations

1.2.9 Memory Management Units (MMUs)

The primary functions of the MMUs are to translate logical (effective) addresses to physical addresses for

memory accesses, I/O accesses (most I/O accesses are assumed to be memory-mapped), and direct-store

accesses, and to provide access protection on blocks and pages of memory.

The PowerPC MMUs and exception model support demand-paged virtual memory. Virtual memory

management permits execution of programs larger than the size of physical memory; demand-paged implies

that individual pages are loaded into physical memory from system memory only when they are first

accessed by an executing program.

The hashed page table is a variable-sized data structure that defines the mapping between virtual page

numbers and physical page numbers. The page table size is a power of 2, and its starting address is a multiple

of its size.

Freescale Semiconductor, Inc.

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