AD9212 datasheet(19/56 Pages) AD

19 / 56 page

AD9212

Rev. 0 | Page 19 of 56

THEORY OF OPERATION

The AD9212 architecture consists of a pipelined ADC that is

divided into three sections: a 4-bit first stage followed by eight

1.5-bit stages and a final 3-bit flash. Each stage provides

sufficient overlap to correct for flash errors in the preceding

stages. The quantized outputs from each stage are combined

into a final 10- result in the digital correction logic. The

pipelined architecture permits the first stage to operate on a

new input sample while the remaining stages operate on preceding

samples. Sampling occurs on the rising edge of the clock.

Each stage of the pipeline, excluding the last, consists of a low

resolution flash ADC connected to a switched-capacitor DAC

and interstage residue amplifier (MDAC). The residue amplifier

magnifies the difference between the reconstructed DAC output

and the flash input for the next stage in the pipeline. One bit of

redundancy is used in each stage to facilitate digital correction

of flash errors. The last stage simply consists of a flash ADC.

The output staging block aligns the data, carries out the error

correction, and passes the data to the output buffers. The data is

then serialized and aligned to the frame and output clock.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD9212 is a differential switched-capacitor

circuit designed for processing differential input signals. The input

can support a wide common-mode range and maintain excellent

performance. An input common-mode voltage of midsupply

minimizes signal-dependent errors and provides optimum

performance.

CPAR

CSAMPLE

CPAR

VIN–

VIN+

Figure 42. Switched-Capacitor Input Circuit

The clock signal alternately switches the input circuit between

sample mode and hold mode (see Figure 42). When the input

circuit is switched into sample mode, the signal source must be

capable of charging the sample capacitors and settling within

one-half of a clock cycle. A small resistor in series with each

input can help reduce the peak transient current injected from

the output stage of the driving source. In addition, low-Q inductors

or ferrite beads can be placed on each leg of the input to reduce

the high differential capacitance seen at the analog inputs, thus

realizing the maximum bandwidth of the ADC. Such use of

low-Q inductors or ferrite beads is required when driving the

converter front end at high IF frequencies. Either a shunt capacitor

or two single-ended capacitors can be placed on the inputs to

provide a matching passive network. This ultimately creates a

low-pass filter at the input to limit any unwanted broadband

noise. See the AN-742 Application Note, the AN-827 Application

Note, and the Analog Dialogue article “Transformer-Coupled

Front-End for Wideband A/D Converters” for more information

on this subject. In general, the precise values depend on the

application.

The analog inputs of the AD9212 are not internally dc-biased.

In ac-coupled applications, the user must provide this bias

externally. Setting the device so that VCM = AVDD/2 is recom-

mended for optimum performance, but the device can function

over a wider range with reasonable performance, as shown in

Figure 45 and Figure 46.

AD9212 Datasheet(PDF) 19 Page - Analog Devices

AD9212 Datasheet(HTML) 19 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

Datasheet Download

Link URL