Preliminary Technical Data

AD9230

Rev. PrE | Page 15 of 21

Figure 16. Single-Ended Input Configuration using SPI enabled CML function

CLOCK INPUT CONSIDERATIONS

For optimum performance, the AD9230 the sample clock inputs

(CLK+ and CLK-) should be clocked with a differential signal.

This signal is typically ac-coupled into the CLK+ and CLK- pins

via a transformer or capacitors. These pins are biased internally

and require no additional bias (See Figure X).

1.2V

CLK+

CLK-

2pF

2pF

AVDD

Figure .Equivalent Clock Input Circuit

Figure X shows one preferred method for clocking the AD9230.

The clock source (low jitter) is converted from single-ended to

differential using an RF transformer. The back-to-back Schottky

diodes across the transformer secondary limit clock excursions

into the AD9230 to approximately 0.8 V p-p differential. This

helps prevent the large voltage swings of the clock from feeding

through to other portions of the AD9230 while preserving the

fast rise and fall times of the signal, which are critical to a low

jitter performance.

Clock

Source

CLK+

CLK-

AD9230

Figure X. Transformer Coupled Differential Clock

If a low jitter clock is available, another option is to ac-couple a

differential PECL signal to the sample clock input pins as shown

in Figure X. The AD9512 (or same family) from offers excellent

jitter performance.

CLK+

CLK-

AD9230

0.1uF

0.1uF

AD9512

PECL

150

Ω

150

Ω

Figure X. Differential PECL Sample Clock

1.25Vp-p

R

49.9

Ω

0.1µF

10µF

0.1uF

AD9230

VIN+

VIN-

AVDD

AGND

CML