PRELIMINARY TECHNICAL DATA

AD9910

Rev. PrD| Page 12 of 13

Figure 6: Linear ramp modulation mode

PARALLEL DATA PORT MODULATION MODE

In parallel data port modulation mode (Figure 7) the modu-

lated DDS signal control parameter(s) are supplied directly

from the 18-bit parallel data port.

The data port is partitioned into two sections. The 16 MSBs make up a 16-bit

data word and the 2 LSBs make up a 2-bit destination word. The destination

word defines how the 16-bit data word is applied to the DDS signal control

parameters.

Table 2 defines the relationship between the destination bits, the

partitioning of the 16-bit data word and the destination of the

data (in terms of the DDS signal control parameters).

NOTE: When the OSK function is enabled, its amplitude data

overrides any parallel port data that is destined for the DDS am-

plitude control parameter.

The sample rate of the parallel data port is ¼ of the DAC sample

rate. The AD9910 generates the PDCLK signal, which is a clock

signal that runs at ¼ of the DAC sample rate and serves as a

data clock. Each rising edge of PDCLK is used to latch the 18

bits of user-supplied data into the data port.

The AD9910 also accepts a user generated TxEn signal that acts

as a gate for the user supplied data. When TxEn is logic 0 the

device ignores the data supplied to the port. However, inter-

nally, the 16-bit data words are either forced to logic zeros or

held at their last state when TxEn transitions from a logic 1 to a

logic 0. The treatment of the 16-bit data words when TxEn is

logic 0 is controlled by a bit in the programming registers. The

destination bits, on the other hand, always retain their last state

when TxEn transitions to a logic 0.

When the destination bits indicate that the data word is des-

tined as a DDS frequency parameter, there is an additional con-

sideration. Recall that the DDS frequency parameter is a 32-bit

word. However, the data word is only 16 bits, which means that

the 16-bit data word must somehow be properly aligned with

the 32-bit frequency parameter. This is accomplished by means

of 4-bit FM Gain word in the programming registers. The FM

Gain word allows the user to apply a weighting factor to the 16-

bit data word.

The default value of the FM Gain word is 0. In the default state,

the data word and the DDS frequency parameter are LSB

aligned. Each increment in the value of the FM Gain word

shifts the 16-bit data word to the left relative to the DDS fre-