LM8333 datasheet(5/17 Pages) NSC

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6.0 Typical Application

6.1 I/O EXPANSION OPTIONS

•

One host-programmable PWM output which also may be

used as a general-purpose output.

•

Four host-programmable general-purpose I/O pins, GE-

N_IO_0, GEN_IO_1, GEN_IO_2, and GEN_IO_3. GE-

N_IO_0 and GEN_IO_1 can also be configured for “slow”

interrupts, in which any transition will trigger a hardware

interrupt event to the host.

6.2 WATCHDOG TIMER

The watchdog timer is always enabled in hardware. To use

the timer, connect the WD_OUT output to the RESET input.

6.3 HALT MODE

The fully static architecture of the LM8333 allows stopping

the internal RC clock in Halt mode, which reduces power

consumption to the minimum level.

Halt mode is entered when no key-press, key-release, or

ACCESS.bus activity is detected for a certain period of time

(by default, 500 milliseconds). The mechanism for entering

Halt mode is always enabled in hardware, but the host can

program the period of inactivity which triggers entry into Halt

mode.

The LM8333 will remain in Active mode as long as a key

event, or any other event, which causes the IRQ output to be

asserted is not resolved.

6.3.1 ACCESS.bus Activity

When the LM8333 is in Halt mode, any activity on the

ACCESS.bus interface will cause the LM8333 to exit from

Halt mode. However, the LM8333 will not be able to ac-

knowledge the first bus cycle immediately following wake-up

from Halt mode. It will respond with a negative acknowledge-

ment, and the host should then repeat the cycle.

The LM8333 will be prevented from entering Halt mode if it

shares the bus with peripherals that are continuously active.

For lowest power consumption, the LM8333 should only

share the bus with peripherals that require little or no bus

activity after system initialization.

20210603

FIGURE 1. Typical Keypad Configuration

LM8333 Datasheet(PDF) 5 Page - National Semiconductor (TI)