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LM8333 Datasheet(PDF) 1 Page - National Semiconductor (TI) |
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LM8333 Datasheet(HTML) 1 Page - National Semiconductor (TI) |
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1 / 17 page ![]() LM8333 Keypad Controller with I/O Expansion and ACCESS.bus Host Interface 1.0 General Description The LM8333 is a general-purpose controller for matrix- addressed keypads which provides an ACCESS.bus (I 2C- compatible) interface to a host microcontroller. It offloads the burden of keyboard scanning from the host, while providing extremely low power consumption in both operational and standby modes. It supports keypad matrices up to8x8in size (plus another 8 special-function keys), for portable ap- plications such as cellphones, PDAs, games, and other handheld applications. Key press and release events are encoded into a byte format and loaded into a FIFO buffer for retrieval by the host pro- cessor. An interrupt output (IRQ) is used to signal events such as keypad activity, a state change on either of two interrupt-capable general-purpose I/O pins, or an error con- dition. Interrupt and error codes are available to the host by reading dedicated registers. Four general-purpose I/O pins are available, two of which have interrupt capability. A pulse-width modulated output based on a host-programmable internal timer is also avail- able, which can be used as a general-purpose output if the PWM function is not required. To minimize power, the LM8333 automatically enters a low- power standby mode when there is no keypad, I/O, or host activity. The device is packaged in a 49-pin MICRO-ARRAY chip- scale package. 2.0 Features n 8 x 8 standard keys n 8 special function keys (SF keys) providing a total of 72 keys for the maximum keyboard matrix n ACCESS.bus (I 2C-compatible) communication interface to the host n Four general purpose host programmable I/O pins with two optional (slow) external Interrupts n 16 byte FIFO buffer to store key pressed and key released events n Error control with error reports on (FIFO overrun, Keypad overrun, invalid command) n Host programmable PWM n Host programmable active time and debounce time 3.0 Block Diagram 20210601 September 2006 © 2006 National Semiconductor Corporation DS202106 www.national.com |
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