LPC86X datasheet(40/99 Pages) NXP

40 / 99 page

LPC86x

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Product data sheet

Rev.3 — 28 April 2023

40 of 97

NXP Semiconductors

LPC86x

32-bit Arm Cortex-M0+ microcontroller

8.25.3 Code Read Protection - CRP

CRP provides different levels of security in the system so that access to the on-chip flash

and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be

restricted. Programming a specific pattern into a dedicated flash location invokes CRP.

IAP commands are not affected by the CRP.

In addition, ISP entry via the ISP entry pin can be disabled without enabling CRP. For

details, see the LPC86x user manual.

There are three levels of Code Read Protection:

1. CRP1 disables access to the chip via the SWD and allows partial flash update

(excluding flash sector 0) using a limited set of ISP commands. This mode is useful

when CRP is required and flash field updates are needed but all sectors cannot be

erased.

2. CRP2 disables access to the chip via the SWD and only allows full flash erase and

update using a reduced set of the ISP commands.

3. Running an application with level CRP3 selected, fully disables any access to the chip

via the SWD pins and ISP. This mode effectively disables ISP override using the ISP

entry pin as well. If necessary, the application must provide a flash update mechanism

using IAP calls or using a call to reinvoke ISP command to enable flash update via the

USART.

In addition to the three CRP levels, sampling of the ISP entry pin for valid user code can

be disabled. For details, see the LPC86x user manual.

8.25.4 APB interface

The APB peripherals are located on one APB bus.

8.25.5 AHBLite

The AHBLite connects the CPU bus of the Arm Cortex-M0+ to the flash memory, the main

static RAM, the CRC, the DMA, the ROM, and the APB peripherals.

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be

performed on the device.

LPC86X Datasheet(PDF) 40 Page - NXP Semiconductors