LPC86X datasheet(71/99 Pages) NXP

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LPC86x

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Product data sheet

Rev.3 — 28 April 2023

71 of 97

NXP Semiconductors

LPC86x

32-bit Arm Cortex-M0+ microcontroller

12.9 Wake-up process

[1]

Typical ratings are not guaranteed. The values listed are at room temperature (25

C), nominal supply

voltages.

[2]

The wake-up time measured is the time between when a GPIO input pin is triggered to wake the device up

from the low power modes and from when a GPIO output pin is set in the interrupt service routine (ISR)

wake-up handler. ISR is located in SRAM.

[3]

FRO enabled, all peripherals off. PLL disabled.

[4]

WKT disabled. Wake up from deep power-down causes the part to go through entire reset

process. The wake-up time measured is the time between when the RESET pin is triggered to wake the

device up and when a GPIO output pin is set in the reset handler.

Table 28.

Dynamic characteristic: Typical wake-up times from low power modes

VDD = 3.3 V;Tamb =25 C; using FRO (24 MHz) as the system clock.

Symbol Parameter

Conditions

Min

Typ[1]

Max Unit

twake

wake-up

time

from sleep mode

[2][3] -1.3

s

from deep-sleep mode

[2] -1.35

s

from power-down mode

[2] -55

s

from deep power-down mode;

WKT disabled; using RESET pin.

[4] -250

s

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