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LPC86X Datasheet(PDF) 65 Page - NXP Semiconductors |
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LPC86X Datasheet(HTML) 65 Page - NXP Semiconductors |
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65 / 99 page  LPC86x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2023. All rights reserved. Product data sheet Rev.3 — 28 April 2023 65 of 97 NXP Semiconductors LPC86x 32-bit Arm Cortex-M0+ microcontroller [1] Cb - total capacitance of the bus line in pF. [2] See tLOW_OD, tfDA_OD, tCF, fSCL. Table 24. MIPI-I3C open drain mode specifications[1] Symbol Parameter Min Max Unit Notes tLOW_OD LOW period of the SCL clock 200 - ns tHIGH HIGH period of the SCL clock - 41 ns tfDA_OD Fall time of SDA signal - 12 ns 2 tSU_OD Data set-up time during open drain mode 3- ns tCAS Clock after START (S) condition ENTAS0 ENTAS1 ENTAS2 ENTAS3 38.4 nano 1 100 2 50 s s ms ms tCBP Clock before STOP (P) condition tCAS(min)/2 - ns tMMOverlap Current master to secondary master overlap time during handoff tDIG_OD_L -ns tAVAL Bus available condition 1 - s tIDLE Bus idle condition 200 - ms tMMLock Time interval where new master not driving SDA low tAVAL - s Table 25. MIPI-I3C push-pull specifications for SDR and HDR-DDR modes[1] Symbol Parameter Min Typ. Max Unit Notes tSCL SCL clock frequency 0.01 12.5 13 MHz tLOW LOW period of the SCL clock 24 - - ns tDIG_L 32 - - ns tHIGH_MIXED HIGH period of the SCL clock for a mixed bus 24 - - ns tDIG_HIGH_M IXED 32 - 45 ns 2 tHIGH HIGH period of the SCL clock 24 - - ns tDIG_H 32 - - ns tSCO Clock in to data out for a target - - 12 tCR SCL clock rise time - - 150e06 * 1 / fSCL (capped at 60) ns tCF SCL clock fall time - - 150e06 * 1 / fSCL (capped at 60) ns tHD_PP SDA signal data hold Controller mode tCR + 3 and tCF +3 -- ns Target mode 0 - - ns |
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