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ADV212 Datasheet(PDF) 12 Page - Analog Devices

Part # ADV212
Description  JPEG 2000 Video Codec
PDF  44 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADV212 Datasheet(HTML) 12 Page - Analog Devices

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ADV212
Rev. 0 | Page 12 of 44
EXTERNAL DMA MODE—FIFO WRITE, BURST MODE
Table 8.
Parameter
Mnemonic
Min
Typ
Max
Unit
DREQ Pulse Width1
DREQPULSE
1 JCLK 2
15 JCLK
ns
WE to DREQ Deassert (DR × PULS = 0)
t
DREQRTN
2.5 JCLK
3.5 × JCLK + 7.5
ns
DACK to WE Setup
t
DACKSU
0
ns
Data Setup
tSU
2.5
ns
Data Hold
tHD
2
ns
WE Assert Pulse Width
WELO
1.5 JCLK
ns
WE Deassert Pulse Width
WEHI
1.5 JCLK
ns
WEDeassert to Next DREQ
t
DREQWAIT
2.5 JCLK
4.5 × JCLK + 9.0
ns
WE Deassert to DACK Deassert
t
WE_DACK
0
ns
1 Applies to assigned DMA channel, if EDMOD0 or EDMOD1 <14:11> is programmed to a nonzero value.
2 For a definition of JCLK, see Figure 32.
DREQ
DACK
WE
HDATA
WEHI
WELO
tDACKSU
tHD
tSU
01
13
14
15
tDREQWAIT
DREQPULSE
tWE_DACK
Figure 13. Burst Write Cycle for DREQ/DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1 <14:11> Not Programmed to a Value of 0000)
DREQ
DACK
WE
WEHI
WELO
tDACKSU
tHD
tSU
0
1
13
14
15
tDREQWAIT
tDREQRTN
HDATA
tWE_DACK
Figure 14. Burst Write Cycle for DREQ/DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1 <14:11> Programmed to a Value of 0000)
DREQ
DACK
WEFB
HDATA
WELO
tDACKSU
tHD
tSU
0
1
13
14
15
tDREQWAIT
WEHI
tWE_DACK
tDREQRTN
Figure 15. Burst Write Cycle for Fly-By DMA Mode



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