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ADV212 Datasheet(PDF) 13 Page - Analog Devices

Part # ADV212
Description  JPEG 2000 Video Codec
PDF  44 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADV212 Datasheet(HTML) 13 Page - Analog Devices

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ADV212
Rev. 0 | Page 13 of 44
EXTERNAL DMA MODE—FIFO READ, BURST MODE
Table 9.
Parameter
Mnemonic
Min
Typ
Max
Unit
DREQ Pulse Width1
DREQPULSE
1 JCLK 2
15 JCLK
ns
RD to DREQ Deassert (DR × PULS = 0)
t
DREQRTN
2.5 JCLK
3.5 × JCLK + 7.5
ns
DACK to RD Setup
t
DACKSU
0
ns
RD to Data Valid
tRD
2.5
9.7
ns
Data Hold
tHD
2.5
ns
RD Assert Pulse Width
RDLO
1.5 JCLK
ns
RD Deassert Pulse Width
RDHI
1.5 JCLK
ns
RD Deassert to Next DREQ
t
DREQWAIT
2.5 JCLK
3.5 × JCLK + 7.5
ns
RD Deassert to DACK Deassert
t
RD_DACK
0
ns
1 Applies to assigned DMA channel if EDMOD0 or EDMOD1 <14:11> is programmed to a nonzero value.
2 For a definition of JCLK, see Figure 32.
DREQ
DACK
HDATA
0
1
13
14
15
tDACKSU
tDREQWAIT
tDREQPULSE
tRD
tHD
tRD_DACK
RD
RDLO
RDHI
Figure 16. Burst Read Cycle for DREQ/DACK DMA Mode for Assigned DMA Channel
(EMOD0/EDMOD1 <14:11> Not Programmed to a Value of 0
DREQ
DACK
HDATA
0
1
13
14
15
tDACKSU
tDREQWAIT
tDREQRTN
tRD
tHD
tRD_DACK
RD
RDLO
RDHI
Figure 17. Burst Read Cycle for DREQ/DACK DMA Mode for Assigned DMA Channel
(EMOD0/EDMOD1 <14:11> Programmed to a Value of 0000)
DREQ
DACK
RDFB
tDACKSU
tHD
tDREQWAIT
HDATA
0
1
13
14
15
tRD
tDREQRTN
tRD_DACK
Figure 18. Burst Read Cycle for Fly-By DMA Mode
RD



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