MPC8347E datasheet(86/108 Pages) FREESCALE

Part #	MPC8347E

Description	Integrated Host Processor Hardware Specifications

PDF	108 Pages

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Manufacturer	FREESCALE [Freescale Semiconductor, Inc]

Direct Link	http://www.freescale.com

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MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3

Freescale Semiconductor

Clocking

19.1

System PLL Configuration

The system PLL is controlled by the RCWL[SPMF] parameter. Table 59 shows the multiplication factor

encodings for the system PLL.

As described in Section 19, “Clocking,” The LBIUCM, DDRCM, and SPMF parameters in the reset

configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the

primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk). Table 60

and Table 61 show the expected frequency values for the CSB frequency for select csb_clk to

CLKIN/PCI_SYNC_IN ratios.

Table 59. System PLL Multiplication Factors

RCWL[SPMF]

System PLL Multiplication

Factor

0000

× 16

0001

Reserved

0010

× 2

0011

× 3

0100

× 4

0101

× 5

0110

× 6

0111

× 7

1000

× 8

1001

× 9

1010

× 10

1011

× 11

1100

× 12

1101

× 13

1110

× 14

1111

× 15

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