TEP datasheet(1/17 Pages) EXXELIA

Part #	TEP

Description	High Capacitance Stacked Capacitors

PDF	17 Pages

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Manufacturer	EXXELIA [Exxelia Group]

Direct Link	https://exxelia.com/en/

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1 / 17 page

CERAMIC CAPACITORS

99

www.exxelia.com

General characteristics

Page revised 02/21

High Capacitance Stacked Capacitors

TEP/TEV Series

HOW TO ORDER

TEP

53

W

F

120nF

±10%

200 V

Series

Exxelia size code

RoHS

compliant

Quality level

Capacitance

Tolerance

Rated voltage

TEP =

radial leads

vertical stack

TEV =

radial leads

horizontal stack

53

54

55

56

57

58

65

- = No RoHS

W = RoHS

compliant

- = standard quality level

F = Hi-Rel quality:

screening in accordance with

Exxelia speciﬁcation

Capacitance value in clear

±1%

±2%

±5%

±10%

±20%

63V

100V

200V

500V

FEATURES

• Multilayer chips ceramic capacitors

• NPO dielectric

• Capacitance range: 10nF to 2.7

µF

• Voltage range: 63 VDC to 500 VDC

PHYSICAL CHARACTERISTICS

CONSTRUCTION

Radial leaded varnished stacked chips capacitors for

through-hole circuits

MARKING (clear or coded)

Series, Capacitance value, tolerance, rated voltage, date

code.

ELECTRICAL SPECIFICATIONS

DIELECTRIC

NPO

Maximum ∆C/°C over temperature range without voltage

NA

Temperature coefﬁcient

(0±30)ppm/°C

Ageing

None

Operating temperature

–55°C to +125°C

Rated voltage (URC)

63 VDC to 500 VDC

Dielectric withstanding voltage

2.5 URC for URC < 500 VDC

2 URC for URC = 500 VDC

Capacitance

at 1kHz

Dissipation factor

≤ 0.15% at 1kHz

Insulation resistance at 25°C under URC

≥ 1,000 MΩ.

µF

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