S71GS256 datasheet(105/195 Pages) SPANSION

105 / 195 page

October 4, 2004 cellRAM_00_A0

CellularRAM Type 2

105

Ad vance

Info rmat i o n

Note: The CLK and ADV# inputs can be tied to VSS if the device is always operating in asynchronous or page mode.

WAIT will be asserted but should be ignored during asynchronous and page mode operations.

Table 15. Signal Descriptions

Symbol

Type

Description

128M: A[22:0]

64M: A[21:0]

32M: A[20:0]

Input

Address Inputs: Inputs for addresses during READ and WRITE operations. Addresses are

internally latched during READ and WRITE cycles. The address lines are also used to define

the value to be loaded into the BCR or the RCR.

CLK

Input

Clock: Synchronizes the memory to the system operating frequency during synchronous

operations. When configured for synchronous operation, the address is latched on the first

rising CLK edge when ADV# is active. CLK is static (HIGH or LOW) during asynchronous

access READ and WRITE operations and during PAGE READ ACCESS operations.

ADV#

Input

Address Valid: Indicates that a valid address is present on the address inputs. Addresses

can be latched on the rising edge of ADV# during asynchronous READ and WRITE

operations. ADV# can be held LOW during asynchronous READ and WRITE operations.

CRE

Input

Configuration Register Enable: When CRE is HIGH, WRITE operations load the RCR or BCR.

CE#

Input

Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and

goes into standby or deep power-down mode.

OE#

Input

Output Enable: Enables the output buffers when LOW. When OE# is HIGH, the output

buffers are disabled.

WE#

Input

Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is a

WRITE to either a configuration register or to the memory array.

LB#

Input

Lower Byte Enable. DQ[7:0]

UB#

Input

Upper Byte Enable. DQ[15:8]

DQ[15:0]

Input/

Output

Data Inputs/Outputs.

WAIT

Output

Wait: Provides data-valid feedback during burst READ and WRITE operations. The signal is

gated by CE#. WAIT is used to arbitrate collisions between refresh and READ/WRITE

operations. WAIT is asserted when a burst crosses a row boundary. WAIT is also used to

mask the delay associated with opening a new internal page. WAIT is asserted and should

be ignored during asynchronous and page mode operations. WAIT is High-Z when CE# is

HIGH.

VCC

Supply

Device Power Supply: (1.7V–1.95V) Power supply for device core operation.

VCCQ

Supply

I/O Power Supply: (1.7V–1.95V) Power supply for input/output buffers.

VSS

Supply

VSS must be connected to ground.

VSSQ

Supply

VSSQ must be connected to ground.

S71GS256 Datasheet(PDF) 105 Page - SPANSION

S71GS256 Datasheet(HTML) 105 Page - SPANSION

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL