S71GS256 datasheet(107/195 Pages) SPANSION

107 / 195 page

October 4, 2004 cellRAM_00_A0

CellularRAM Type 2

107

Ad vance

Info rmat i o n

Notes:

1. CLK may be HIGH or LOW, but must be static during asynchronous read, synchronous write, burst suspend, and

DPD modes; and to achieve standby power during standby and active modes.

2. The WAIT polarity is configured through the bus configuration register (BCR[10]).

3. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When only LB# is in select mode, DQ[7:0]

are affected. When only UB# is in the select mode, DQ[15:8] are affected.

4. The device will consume active power in this mode whenever addresses are changed.

5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any

external influence.

6. VIN = VCCQ or 0V; all device balls must be static (unswitched) to achieve standby current.

7. DPD is maintained until RCR is reconfigured.

8. Burst mode operation is initialized through the bus configuration register (BCR[15]).

Functional Description

The CellularRAM bus interface supports both asynchronous and burst mode

transfers. Page mode accesses are also included as a bandwidth-enhancing ex-

tension to the asynchronous read protocol.

Power-Up Initialization

CellularRAM products include an on-chip voltage sensor used to launch the

power-up initialization process. Initialization will configure the BCR and the RCR

with their default settings (see Table 18 and Table 22). VCC and VCCQ must be

applied simultaneously. When they reach a stable level at or above 1.7V, the de-

vice will require 150µs to complete its self-initialization process. During the

initialization period, CE# should remain HIGH. When initialization is complete, the

device is ready for normal operation.

Table 17. Bus Operations—Burst Mode

MODE

POWER

CLK

(Note 1) ADV#

CE#

OE#

WE#

CRE

LB#/

UB#

WAIT

(Note 2)

DQ[15:0]

(Note 3)NOTES

Async Read

Active

Low-Z

Data-Out

Async Write

Active

Low-Z

Data-In

Standby

High-Z

5, 6

No Operation

Idle

Low-Z

4, 6

Initial Burst Read

Active

Low-Z

Data-Out

4, 8

Initial Burst Write

Active

Low-Z

Data-In

4, 8

Burst Continue

Active

Low-Z

Data-In or

Data-Out

4, 8

Burst Suspend

Active

Low-Z

High-Z

4, 8

Configuration

Active

Low-Z

High-Z

DPD

Deep

Power-Down

XXXX

High-Z

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